LMH1982 Datasheet, PDF (1/28 Pages) National Semiconductor (TI) – Multi-Rate Video Clock Generator with Genlock

PRELIMINARY
April 9, 2008
LMH1982
Multi-Rate Video Clock Generator with Genlock
General Description
The LMH1982 is a multi-rate video clock generator ideal for
use in a wide range of 3-Gbps (3G), high-definition (HD), and
standard-definition (SD) video applications, such as video
synchronization, serial digital interface (SDI) serializer and
deserializer (SerDes), video conversion, video editing, and
other broadcast and professional video systems.
The LMH1982 can generate two simultaneous SD and HD
clocks and a Top of Frame (TOF) pulse. In genlock mode, the
device's phase locked loops (PLLs) can synchronize the out-
put signals to H sync and V sync input signals applied to either
of the reference ports. The input reference can have analog
timing from National's LMH1981 multi-format video sync sep-
arator or digital timing from an SDI deserializer and should
conform to the major SD and HD standards. When a loss of
reference occurs, the device can default to free run operation
where the output timing accuracy will be determined by the
external bias on the free run control voltage input.
The LMH1982 can replace discrete PLLs and field-pro-
grammable gate array (FPGA) PLLs with multiple voltage
controlled crystal oscillators (VCXOs). Only one 27.0000 MHz
VCXO and loop filter are externally required for genlock
mode. The external loop filter as well as programmable PLL
parameters can provide narrow loop bandwidths to minimize
jitter transfer. HD clock output jitter as low as 40 ps peak-to-
peak can help designers using FPGA serializers meet strin-
gent SDI output jitter specifications.
The LMH1982 is offered in a space-saving 5 mm x 5 mm 32-
pin LLP package and provides low total power dissipation of
250 mW (typical).
Features
■ ^{Two simultaneous LVDS output clocks with selectable}
frequencies and Hi-Z capability:
— SD clock: 27 MHz or 67.5 MHz
— HD clock: 74.25 MHz, 74.25/1.001 MHz, 148.5 MHz or
148.5/1.001 MHz
■ ^{Low-jitter output clocks may be directly connected to an}
FPGA serializer to meet SMPTE SDI jitter specifications
■ ^{Top of Frame (TOF) pulse with programmable output}
format timing and Hi-Z capability
■ ^{Two reference ports (A and B) with H and V sync inputs}
■ ^{Supports cross-locking of input and output timing}
■ ^{External loop filter allows control of loop bandwidth, jitter}
transfer, and lock time characteristics
■ ^{Free run or Holdover operation on loss of reference}
■ ^{User-defined free run control voltage input}
■ ^{I2C interface and control registers}
■ ^{3.3V and 2.5V supplies}
Applications
■ ^{Video genlock and synchronization}
■ ^{Triple rate 3G/HD/SD-SDI SerDes}
■ ^{Video capture, conversion, editing and distribution}
■ ^{Video displays and projectors}
■ ^{Broadcast and professional video equipment}
Typical System Block Diagram
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