LMH1982 Datasheet, PDF (4/28 Pages) National Semiconductor (TI) – Multi-Rate Video Clock Generator with Genlock

Table of Contents
General Description .............................................................................................................................. 1
Features .............................................................................................................................................. 1
Applications ......................................................................................................................................... 1
Typical System Block Diagram ............................................................................................................... 1
Functional Block Diagram ...................................................................................................................... 2
Ordering Information ............................................................................................................................. 2
Connection Diagram ............................................................................................................................. 3
Absolute Maximum Ratings .................................................................................................................... 6
Operating Ratings ................................................................................................................................ 6
Electrical Characteristics ........................................................................................................................ 6
Typical Performance Characteristics ....................................................................................................... 8
Application Information .......................................................................................................................... 9
1.0 FUNCTIONAL OVERVIEW ............................................................................................................. 9
2.0 GENERAL PROGRAMMING INFORMATION ................................................................................... 9
2.1 Recommended Start-Up Programming Sequence ............................................................................ 9
2.2 Enabling Genlock Mode ............................................................................................................... 9
2.3 Output Disturbance While Alignment Mode Enabled ......................................................................... 9
3.0 MODES OF OPERATION ............................................................................................................. 10
3.1 Free Run Mode ......................................................................................................................... 10
3.2 Genlock Mode ........................................................................................................................... 10
3.2.1 Genlock Mode State Diagram ................................................................................................. 10
3.2.2 Loss of Reference (LOR) ..................................................................................................... 10
3.2.2.1 Free Run during LOR ..................................................................................................... 10
3.2.2.2 Holdover during LOR ...................................................................................................... 10
3.3 Recognized Video Timing Formats And Standards ......................................................................... 11
4.0 INPUT REFERENCE ................................................................................................................... 13
4.1 Programming The VCXO PLL Dividers ......................................................................................... 13
4.2 Internal Reference Frame Decoder .............................................................................................. 13
5.0 OUTPUT CLOCKS AND TOF ....................................................................................................... 13
5.1 Programming The Output Clock Frequencies ................................................................................ 13
5.2 Programming The Output Timing Format ...................................................................................... 14
5.2.1 Output Clock Reference ......................................................................................................... 14
5.2.2 Output Frame Rate ............................................................................................................... 14
5.2.3 Reference Frame Rate .......................................................................................................... 14
5.2.4 Input-Output Frame Rate Ratio ............................................................................................... 14
5.2.5 Output Frame Line Offset ....................................................................................................... 14
5.3 Programming The Output Alignment Sequence ............................................................................. 15
5.3.1 Output Clock Alignment without TOF ....................................................................................... 15
5.4 Output Behavior Upon Loss Of Reference .................................................................................... 15
6.0 REFERENCE AND PLL LOCK STATUS ......................................................................................... 16
6.1 Reference Detection .................................................................................................................. 16
6.1.1 Programming the Loss of Reference (LOR) Threshold ............................................................... 16
6.2 PLL Lock Detection ................................................................................................................... 16
6.2.1 Programming the PLL Lock Threshold ..................................................................................... 16
6.2.2 PLL Lock Status Instability ..................................................................................................... 17
7.0 VCXO PLL LOOP RESPONSE .................................................................................................... 17
7.1 Loop Response Design Equations ............................................................................................... 17
7.1.1 Loop Response Optimization Tips ........................................................................................... 17
7.2 Lock Time Considerations .......................................................................................................... 18
7.3 VCXO Considerations ................................................................................................................ 18
7.4 Free Run Output Jitter ................................................................................................................ 18
8.0 I²C INTERFACE PROTOCOL ....................................................................................................... 18
8.1 Write Sequence ........................................................................................................................ 18
8.2 Read Sequence ........................................................................................................................ 18
8.3 I²C Enable Control Pin .............................................................................................................. 19
9.0 I²C INTERFACE CONTROL REGISTER DEFINITIONS ................................................................... 19
9.1 Genlock And Input Reference Control Registers ............................................................................ 20
9.2 Genlock Status And Lock Control Register .................................................................................... 20
9.3 Input Control Register ................................................................................................................ 20
9.4 PLL 1 Divider Register ............................................................................................................... 21
9.5 PLL 4 Charge Pump Current Control Registers .............................................................................. 21
9.6 Output Clock And TOF Control Register ....................................................................................... 21
9.7 TOF Configuration Registers ....................................................................................................... 21
9.8 PLL 1 Charge Pump Current Control Register ............................................................................... 22
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