LMH1982 Datasheet, PDF (7/28 Pages) National Semiconductor (TI) – Multi-Rate Video Clock Generator with Genlock

Clock Outputs (Pins 19, 20, 23, 24)
Jitter_SD 27 MHz Time Interval Error
(TIE) Peak-to-Peak Output
Jitter (Note 5)
HD_CLK = Hi-Z
27 MHz TIE Peak-to-Peak
Output Jitter(Note 5)
HD_CLK = 74.176 MHz
67.5 MHz TIE Peak-to-Peak
Output Jitter (Note 5)
HD_CLK = 74.176 MHz
Jitter_HD 74.176 MHz TIE Peak-to-Peak SD_CLK = Hi-Z
Output Jitter (Note 5)
74.25 MHz TIE Peak-to-Peak SD_CLK = Hi-Z
Output Jitter (Note 5)
148.35 MHz TIE Peak-to-Peak SD_CLK = Hi-Z
Output Jitter (Note 5)
148.5 MHz TIE Peak-to-Peak SD_CLK = Hi-Z
Output Jitter (Note 5)
V_OD Differential Signal Output
Voltage
100Ω Differential Load
V_OS
|V_OD|
Common Signal Output Voltage 100Ω Differential Load
|Change to V_OD| for
100Ω Differential Load
Complementary Output States
|V_OS| |Change to V_OS| for
100Ω Differential Load
Complementary Output States
I_OS Output Short Circuit Current V_CLK and V_CLK = GND
I_OZ Output Hi-Z Leakage Current CLK = Hi-Z, V_CLK = V_DD or GND
23
ps
40
50
55
40
60
45
247
350
454
1.125
1.250
1.375
50
50
24
1
10
ps
ps
ps
ps
ps
ps
mV
V
|mV|
|mV|
|mA|
|µA|
Note 1: Absolute Maximum Ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions under which operation of the
device is intended to be functional. For guaranteed specifications and test conditions, see the Electrical Characteristics.
Note 2: Human Body Model, applicable std. MIL-STD-883, Method 3015.7. Machine Model, applicable std. JESD22-A115-A (ESD MM std. of JEDEC)
Field-Induced Charge-Device Model, applicable std. JESD22-C101-C (ESD FICDM std. of JEDEC).
Note 3: The input voltage to VC_FREERUN (pin 1) should also be within the input range of the external VCXO. The input voltage should be clean from noise
that may significantly modulate the VCXO control voltage and consequently produce output jitter during free run operation.
Note 4: ΔT_HV is required specification to allow for proper frame decoding and subsequent output alignment. For interlace formats, the H-V timing offset must be
within ΔT_HV for all even fields and be outside ΔT_HV for odd fields. For progressive formats, the H-V timing offset must be within ΔT_HV for all frames. See sections
4.2 Internal Reference Frame Decoder and 5.2.5 Output Frame Line Offset.
Note 5: The SD and HD clock output jitter is based on VCXO clock with 20 ps TIE peak-to-peak jitter. The TIE peak-to-peak jitter (typical) was measured on the
LMH1982 evaluation bench board using a Tektronix DSA70604 oscilloscope with TDSJIT3 jitter analysis software and 1 GHz differential probe.
TIE Measurement Setup: 10^-12 bit error rate (BER) and ≈1M samples recorded over multiple acquisitions. The number of acquisitions to record ≈1M samples
varied with clock frequency.
Oscilloscope Setup: 20 mV/div vertical scale, 100 us/div horizontal scale, and 25 Gs/s sampling rate.
7
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