LMH1982 Datasheet, PDF (15/28 Pages) National Semiconductor (TI) – Multi-Rate Video Clock Generator with Genlock

ment sequence. The line offset value programmed to
TOF_OFFSET can delay or advance the output alignment
relative to the reference line where the input H and V pulse
are within ΔT_HV (see section 4.2 Internal Reference Frame
Decoder).
TOF_OFFSET must be greater than zero but less than or
equal to the total lines per reference frame. If no line offset is
required, then set TOF_OFFSET equal to REF_LPFM in-
stead of zero (invalid).
TABLE 7. TOF Line Offset Selection
Register 11h-12h
TOF_OFFSET
Line Offset Value for
Output Alignment
0...00
Invalid
0...01
1
:
:
1...10
4094
1...11
4095
For example, if an input reference with PAL timing comes from
the LMH1981, the H and V pulses will be aligned to within
ΔT_HV for the even field V pulses which occur on line 313 of
the reference. In this case, TOF_OFFSET can be set to 312d
so the output frame will align to Line 1 of the PAL reference
(start of frame) after the output alignment is subsequently im-
plemented. This example is illustrated in Figure 5.
30052434
FIGURE 5. PAL Reference and Output TOF Pulse
(TOF_OFFSET = 312)
5.3 Programming The Output Alignment Sequence
Before implementing the output alignment sequence, the fol-
lowing prerequisites must be met as described:
1. The VCXO PLL must be stable and locked to the input
reference.
2. The desired output clock and TOF pulse timing must be
fully specified to the output format registers.
To ensure that the output clock and TOF pulse are properly
aligned and subsequently phas locked to the reference frame,
the output alignment sequence should be programmed ac-
cordingly.
During the output frame immediately prior to the frame the
alignment is to occur:
1. Set EN_TOF_RST = 1(register 0Ah) to enable output
alignment mode.
2. Toggle TOF_INIT (register 0Ah) from 0 to 1 to initialize
the internal counters. On the next frame, the output clock
and TOF pulse will be aligned to the reference frame and
relative line offset based on TOF_OFFSET.
3. Immediately after the alignment and before the next
output frame occurs, clear EN_TOF_RST and TOF_INIT
to 0. Otherwise, the output clock will be continually
aligned every output frame, which may cause excessive
jitter on the output clock due to slight differences in the
reset timing of the internal counters. This occurrence of
excessive clock jitter can be avoided by disabling output
alignment mode (EN_TOF_RST = 0) immediately after
the alignment.
Note: Due to the following conditions, the TOF pulse may be
delayed or offset by more than one pixel clock (t_OD > 1 pixel
clock) even after the output alignment sequence:
1. The H sync and/or V sync input pulses have excessive
jitter equal to or larger than half of a pixel period of the
selected output clock. Input sync jitter less than 3 ns
peak-to-peak is recommended.
2. The VCXO PLL is not completely phase locked nor stable
when the output alignment is performed.
5.3.1 Output Clock Alignment without TOF
For applications that do not require the TOF pulse, it is still
necessary to program all output format registers prior to the
output alignment sequence. This is because the output align-
ment circuitry relies on the full and correct specification of the
output format. If the TOF output is not needed, it can be put
in Hi-Z mode by setting TOF_HIZ = 1 (register 08h).
5.4 Output Behavior Upon Loss Of Reference
After loss of reference (LOR), the LMH1982 will maintain the
TOF pulse without the input reference according to the ter-
minal counts of the reference clock; however, output frequen-
cy accuracy will be determined by the VCXO, which may be
in Free Run or Holdover operation.
To disable output alignment to an arbitrary reference frame
when the reference is reapplied, set EN_TOF_RST = 0 before
the reference returns. After the VCXO PLL has re-locked to
the reference, the outputs can be initialized to the desired ref-
erence frame.
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