LMH1982 Datasheet, PDF (3/28 Pages) National Semiconductor (TI) – Multi-Rate Video Clock Generator with Genlock

Connection Diagram
Top View
30052402
Pin Descriptions
Pin No.
Pin Name
I/O
–
DAP
–
1
VC_FREERUN
I
2, 10, 18, 22, 26, 30
GND
–
3, 21, 27, 28, 32
V_DD
–
4
HREF_A
I
5
VREF_A
I
6
REF_SEL
I
7
HREF_B
I
8
VREF_B
I
9
DV_DD
–
11
SDA
I/O
12
SCL
I
13
I²C_ENABLE
I
14
GENLOCK
I
15
RESET
I
16
NO_REF
O
17
NO_LOCK
O
19, 20
HD_CLK, HD_CLK
O
23, 24
SD_CLK, SD_CLK
O
25
TOF
O
29
VCXO
I
31
LPF
O
Signal Level
Supply
Analog
Supply
Supply
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
Supply
I²C
I²C
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVDS
LVDS
LVCMOS
LVCMOS
Analog
Pin Description
Die Attach Pad (Connect to GND)
Free Run Control Voltage Input
Ground
3.3V Supply
H sync Input, Reference A
V sync Input, Reference A
Reference Select ^{1, 2}
H sync Input, Reference B
V sync Input, Reference B
2.5V Supply
I²C Data ³
I²C Clock ³
I²C Enable
Mode Select ⁴
Device Reset
Reference Status Flag
Lock Status Flag
HD Clock Output
SD Clock Output
Top of Frame Pulse
VCXO Clock Input
VCXO PLL Loop Filter
Notes
1. To control reference selection via the REF_SEL input pin instead of the I²C interface (default), program I²C_RSEL = 0 (register 00h).
2. To override reference control via pin 6 and instead use pin 6 as an logic pulse input for output alignment initialization, program PIN6_OVRD = 1 (register 02h).
Consequently, reference selection must be controlled via I²C, and the TOF_INIT bit (register 0Ah) will be ignored.
3. SDA and SCL pins each require a 4.7kΩ (typ.) pull-up resistor to the V_DD supply.
4. To control mode selection via the GENLOCK input pin instead of the I²C interface (default), program I²C_GNLK = 0 (register 00h).
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