LMH1982 Datasheet, PDF (19/28 Pages) National Semiconductor (TI) – Multi-Rate Video Clock Generator with Genlock

The subsequent read data transfer shown in Figure 8 consists
of a start pulse, the slave device address including the read/
write bit (a one, indicating a read) and the ACK bit. The next
byte is the data read from the initial access address. Subse-
quent read data bytes will correspond to the next increment
address locations. Each data byte is separated from the other
data bytes by an ACK bit.
FIGURE 8. LMH1982 Read Sequence – Data Read Transfer
30052406
8.3 I²C Enable Control Pin
When the active low input I²C_ENABLE = 0, the LMH1982
will enable I²C communication via its fixed slave address;
otherwise, the LMH1982 will not respond. For applications
with multiple LMH1982 devices on the same I²C bus, the I²C
9.0 I²C INTERFACE CONTROL REGISTER DEFINITIONS
enable function can be useful for writing data to a specific
device(s) and for reading data from an individual device to
prevent bus contention. For single chip applications, the
I2C_ENABLE input can be tied to GND to keep the I²C inter-
face enabled.
TABLE 10. I²C Interface Control Register Map
Register Default D7
D6
D5
D4
D3
D2
D1
D0
Address Data
00h
A3h GNLK_I²C GNLK RSEL_I²C RSEL
HOLD-
OVER
H_ERROR [2:0]
01h
86h
LOCK_CTRL [7:3]
HD_LOCK SD_LOCK REF_VALID
02h
00h
RSV
RSV
PIN6_
OVRD
REF_27 POL_HA POL_VA POL_HB
POL_VB
03h
01h
RSV
RSV
RSV
RSV
RSV
RSV
REF_DIV [1:0]
04h
B4h
FB_DIV [7:0]
05h
06h
0
0
0
FB_DIV [12:8]
06h
00h
RSV
RSV
RSV
RSV
ICP4 [3:0]
07h
00h
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
08h
04h
RSV
RSV TOF_HIZ HD_HIZ
HD_FREQ [3:2]
SD_HIZ SD_FREQ
09h
01h
TOF_RST [7:0]
0Ah
00h EN_TOF_ POL_TOF TOF_INIT
RST
TOF_RST [12:8]
0Bh
B4h
TOF_PPL [7:0]
0Ch
06h
0
0
TOF_CLK
TOF_PPL [12:8]
0Dh
0Dh
TOF_LPFM [7-0]
0Eh
02h
0
0
0
0
TOF_LPFM [11:8
0Fh
0Dh
REF_LPFM [7-0]
10h
02h
0
0
0
0
REF_LPFM [11:8]
11h
00h
TOF_OFFSET [7-0]
12h
00h
0
0
0
0
TOF_OFFSET [11:8]
13h
88h
RSV
RSV
RSV
ICP1 [4:0]
14h
88h
ICP2 [7:4]
ICP3 [3:0]
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