LMH1982 Datasheet, PDF (23/28 Pages) National Semiconductor (TI) – Multi-Rate Video Clock Generator with Genlock

ICP1 = 8: 250 µA nominal (default)
ICP1 = 31: 1000 µA nominal
ICP1 step: 31.25 µA nominal current step
Bits 7-5: Reserved (RSV)
9.9 PLL 2 and PLL 3 Charge Pump Current Control
Register
REGISTER 14h
Bits 3-0: Charge Pump Current Control for PLL 3 (ICP3)
ICP3 can be programmed to specify the charge pump current
for PLL 3, which generates the 74.176 and 148.35 MHz HD
clock outputs. Reducing the value of ICP3 will reduce the PLL
3 charge pump current and lower its loop bandwidth at the
expense of reduced PLL stability. An value of 0 should not be
programmed since this corresponds to 0 µA nominal current
and will cause PLL 3 to lose phase lock.
Bit 7-4: Charge Pump Current Control for PLL 2 (ICP2)
ICP2 can be programmed to specify the charge pump current
for PLL 2, which generates the 74.25 and 148.5 MHz HD clock
outputs. Reducing the value of ICP2 will reduce the PLL 2
charge pump current and lower its loop bandwidth at the ex-
pense of reduced PLL stability. An value of 0 should not be
programmed since this corresponds to 0 µA nominal current
and will cause PLL 2 to lose phase lock.
9.10 Reserved Registers
REGISTER 07h
REGISTER 15h-1Fh
Do not program any data to these registers.
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