PC87363 Datasheet, PDF (72/200 Pages) National Semiconductor (TI) – 128-Pin LPC SuperI/O with MIDI and Game Ports, Extended Wake-Up and Protection

2.0 Device Architecture and Configuration (Continued)
2.17.3 Fan Speed Control and Monitor Configuration 1 Register
This register is reset by hardware to 00h.
Location: Index F0h
Type:
R/W
Bit
Name
Reset
7
6
5
4
3
2
Fan Speed Fan Speed Fan Speed Fan Speed Fan Speed Fan Speed
Invert 1 Control 1 Monitor 1 Invert 0 Control 0 Monitor 0
Enable
Enable
Enable
Enable
Enable
Enable
0
0
0
0
0
0
1
Reserved
0
0
TRI-STATE
Control
0
Bit
Description
7 Fan Speed Invert 1 Enable
0: Disabled (default)
1: Enabled
6 Fan Speed Control 1 Enable
0: Disabled (default)
1: Enabled
5 Fan Speed Monitor 1 Enable
0: Disabled (default)
1: Enabled
4 Fan Speed Invert 0 Enable
0: Disabled (default)
1: Enabled
3 Fan Speed Control 0 Enable
0: Disabled (default)
1: Enabled
2 Fan Speed Monitor 0 Enable
0: Disabled (default)
1: Enabled
1 Reserved
0 TRI-STATE Control. When enabled and the device is inactive, the logical device output pins are in TRI-STATE.
0: Disabled (default)
1: Enabled
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