PC87363 Datasheet, PDF (154/200 Pages) National Semiconductor (TI) – 128-Pin LPC SuperI/O with MIDI and Game Ports, Extended Wake-Up and Protection

9.0 Game Port (GMP) (Continued)
9.3.2 Game Port Control Register (GMPCTL)
This register affects the functionality of the Game Port only when operated in Enhanced mode (bit 0 of this register is set
to 1). Bits 1,2 and 4-7 affect Game Port functionality, as described in the table below.
Location: Offset 00h
Type:
R/W
Bit
Name
Reset
Required
7
6
5
4
Device B
Button 1
Debounce
Enable
Device B
Button 0
Debounce
Enable
Device A
Button 1
Debounce
Enable
Device A
Button 0
Debounce
Enable
0
0
0
0
3
Reserved
0
0
2
Device B
Pre-Scale
Enable
0
1
Device A
Pre-Scale
Enable
0
0
GMP
Enhanced
Mode
Enable
0
Bit
Description
7 Device B Button 1 Debounce Enable. When set to 1, enables a 16 ms input debouncer on Device B Button 1
status input.
0: Disabled (default)
1: Enabled
6 Device B Button 0 Debounce Enable. Same as bit 7, but for Device B Button 0.
0: Disabled (default)
1: Enabled
5 Device A Button 1 Debounce Enable. Same as bit 7, but for Device A Button 1.
0: Disabled (default)
1: Enabled
4 Device A Button 0 Debounce Enable. Same as bit 7, but for Device A Button 0.
0: Disabled (default)
1: Enabled
3 Reserved
2 Device B Pre-Scale Enable. This bit determines the clock frequency used by Device B position counters.
0: 1 MHz (default)
1: 500 KHz
1 Device A Pre-Scale Enable. This bit determines the clock frequency used by Device A position counters.
0: 1 MHz (default)
1: 500 KHz
0 GMP Enhanced Mode Enable
0: Disabled (default)
1: Enabled
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