PC87363 Datasheet, PDF (112/200 Pages) National Semiconductor (TI) – 128-Pin LPC SuperI/O with MIDI and Game Ports, Extended Wake-Up and Protection

3.0 System Wake-Up Control (SWC) (Continued)
3.4.33 Standby GPIOE/GPIE Data Out Register 0 (SB_GPDO0)
This register is set to 3Fh on V_PP power-up or software reset, only when the Lock bit of the SBGPCFG register is set to 0.
It determines the value to be driven on the GPIOE pins when configured as outputs.
Location: Offset 08h
Type:
R/W
Bit
Name
Reset
7
6
5
4
3
2
1
0
Reserved
Data Out
0
0
1
1
1
1
1
1
Bit
Description
7-6 Reserved
5
Data Out. Bits 5-0 correspond to pins GPIOE5-0 respectively. The value of each bit determines the value driven
4 _{on the corresponding GPIOE pin when its output buffer is enabled. Writing to the bit latches the written data}
3 unless the bit is locked by the corresponding GPIOE Configuration Lock bit. Reading the bit returns its value,
2 ^{regardless of the pin value and configuration.}
0: Corresponding pin level low when output enabled
1
1: Corresponding pin level high (according to buffer type and static pull-up selection) when output enabled
0
3.4.34 Standby GPIOE/GPIE Data In Register 0 (SB_GPDI0)
This register reflects the values of the GPIE7-6 and GPIOE5-0 pins. Write to this register is ignored.
Location: Offset 09h
Type:
RO
Bit
Name
Reset
7
6
5
4
3
2
1
0
Data In
X
X
X
X
X
X
X
X
Bit
Description
7
6
5 _{Data In. Bits 7-0 correspond to pins GPIE7-6 and GPIOE5-0 respectively. Reading each bit returns the value of}
4 the corresponding GPIE/GPIOE pin regardless of the pin configuration and the SB0_GPDO register value.
3 ^{0: Corresponding pin level low}
2 ^{1: Corresponding pin level high}
1
0
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