PC87363 Datasheet, PDF (147/200 Pages) National Semiconductor (TI) – 128-Pin LPC SuperI/O with MIDI and Game Ports, Extended Wake-Up and Protection

8.0 ACCESS.bus Interface (ACB) (Continued)
8.3.6 ACB Own Address Register (ACBADDR)
This is a byte-wide register that holds the ACB ACCESS.bus address. The reset value of this register is undefined.
Location: Offset 04h
Type:
R/W
Bit
7
6
5
4
3
2
1
0
Name
SAEN
ADDR
Reset
Bit
Description
7 SAEN (Slave Address Enable)
0: ACB does not check for an address match with ADDR field
1: ADDR field holds a valid address and enables the match of ADDR to an incoming address byte
6-0 ADDR (Own Address). These bits hold the 7-bit device address. When in slave mode, the first 7 bits received
after a Start Condition are compared with this field (first bit received is compared with bit 6, and the last bit with
bit 0). If the address field matches the received data and SAEN (bit 7) is 1, a match is declared.
8.3.7 ACB Control Register 2 (ACBCTL2)
This register enables/disables the functional block and determines the ACB clock rate.
Location: Offset 05h
Type:
R/W
Bit
Name
Reset
7
6
5
4
3
2
SCLFRQ
0
0
0
0
0
0
1
0
ENABLE
0
0
Bit
Description
7-1 SCLFRQ (SCL Frequency). This field defines the SCL period (low and high time) when the device serves as a
bus master. The clock low and high times are defined as follows:
t_SCLl = t_SCLh = 2*SCLFRQ*t_CLK
where t_CLK is the module input clock cycle, as defined in the Device Architecture and Configuration chapter.
SCLFRQ can be programmed to values in the range of 0001000₂ (8₁₀) through 1111111₂ (127₁₀). Using any
other value has unpredictable results.
0 Enable
0: ACB disabled, ACBCTL1, ACBST and ACBCST cleared, and clocks halted
1: ACB enabled
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