PC87363 Datasheet, PDF (102/200 Pages) National Semiconductor (TI) – 128-Pin LPC SuperI/O with MIDI and Game Ports, Extended Wake-Up and Protection

3.0 System Wake-Up Control (SWC) (Continued)
3.4.23 CEIR Wake-Up Address Register (IRWAD)
This register holds the unique address to be compared with the address contained in the incoming CEIR message. If CEIR
is enabled (bit 0 of the IRWCR register is 1) and an address match occurs, then bit 5 of the WK0_STS register is set to 1
(see Section 3.4.2).
This register is set to 00h on power-up of V_PP or software reset.
Location: Bank 1, Offset 15h
Type:
R/W
Bit
Name
Reset
7
6
5
4
3
2
1
0
CEIR Wake-Up Address
0
0
0
0
0
0
0
0
3.4.24 CEIR Wake-Up Address Mask Register (IRWAM)
Each bit in this register determines whether the corresponding bit in the IRWAD register is enabled in the address compar-
ison. Bits 5, 6 and 7 must be set to 1 if the RC-5 protocol is selected.
This register is set to E0h on power-up of V_PP or software reset.
Location: Bank 1, Offset 16h
Type:
R/W
Bit
Name
Reset
7
6
5
4
3
2
1
0
CEIR Wake-Up Address Mask
1
1
1
0
0
0
0
0
Bit
Description
7-0 CEIR Wake-Up Address Mask. If the corresponding bit is 0, the address bit is not masked (enabled for
compare). If the corresponding bit is 1, the address bit is masked (ignored during compare).
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