PC87363 Datasheet, PDF (175/200 Pages) National Semiconductor (TI) – 128-Pin LPC SuperI/O with MIDI and Game Ports, Extended Wake-Up and Protection

11.0 Legacy Functional Blocks (Continued)
11.3 PARALLEL PORT
11.3.1 General Description
The Parallel Port supports all IEEE1284 standard communication modes: Compatibility (known also as Standard or SPP),
Bidirectional (known also as PS/2), FIFO, EPP (known also as Mode 4) and ECP (with an optional Extended ECP mode).
11.3.2 Parallel Port Register Map
The Parallel Port functional block register maps are grouped according to first and second level offsets. EPP and second
level offset registers are available only when base address is 8-byte aligned.
Table 48. Parallel Port Register Map for First Level Offset
First Level
Offset
Mnemonic
Register Name
000h
000h
001h
002h
003h
004h
005h
006h
007h
400h
400h
400h
400h
401h
402h
403h
404h
405h
DATAR PP Data
AFIFO ECP Address FIFO
DSR Status
DCR Control
ADDR EPP Address
DATA0 EPP Data Port 0
DATA1 EPP Data Port 1
DATA2 EPP Data Port 2
DATA3 EPP Data Port 3
CFIFO PP Data FIFO
DFIFO ECP Data FIFO
TFIFO Test FIFO
CNFGA Configuration A
CNFGB Configuration B
ECR Extended Control
EIR Extended Index
EDR Extended Data
EAR Extended Auxiliary Status
Modes (ECR Bits)
765
Type
000
001
R/W
011
W
All Modes
RO
All Modes
R/W
100
R/W
100
R/W
100
R/W
100
R/W
100
R/W
010
W
011
R/W
110
R/W
111
RO
111
RO
All Modes
R/W
All Modes
R/W
All Modes
R/W
All Modes
R/W
Table 49. Parallel Port Register Map for Second Level Offset
Second Level
Offset
Register Name
Type
00h
Control0
R/W
02h
Control2
R/W
04h
Control4
R/W
05h
PP Confg0 R/W
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