PC87363 Datasheet, PDF (47/200 Pages) National Semiconductor (TI) – 128-Pin LPC SuperI/O with MIDI and Game Ports, Extended Wake-Up and Protection

2.0 Device Architecture and Configuration (Continued)
2.8.6 SuperI/O Configuration 5 Register (SIOCF5)
Location: Index 25h
Type:
Varies per bit
Bit
7
6
5
4
Name
Reserved
SMI to IRQ2
Enable
Reset
0
0
0
0
3
2
Reserved
0
0
Bit
7-5 Reserved
4 SMI to IRQ2 Enable. This is a R/W bit.
0: Disabled (default)
1: Enabled
3-2 Reserved
1-0 Pin 128 Function Select. This is a RO bit.
Bits
1 0 Function
0 0 GPIO33 (default)
Others Reserved
Description
1
0
Pin 128
Function
Select
0
0
2.8.7 SuperI/O Revision ID Register (SRID)
This register contains the identity number of the chip revision. SRID is incremented on each revision.
Location: Index 27h
Type:
RO
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