PC87363 Datasheet, PDF (40/200 Pages) National Semiconductor (TI) – 128-Pin LPC SuperI/O with MIDI and Game Ports, Extended Wake-Up and Protection

2.0 Device Architecture and Configuration (Continued)
nipulates the PWBTOUT so that the ACPI controller is always synchronized with the actual state of the PSON output. This
synchronization mechanism assumes that PWBTOUT is connected to the power button input of the ACPI controller. See a
schematic state diagram of the Legacy PSC mechanism in Figure 4.
VSB
Power-Up
Reset
Power
Fail
Resume AND Last State is ON
VSB Present AND Straps Sampled
Check
Resume
Mode
No Resume AND ACPI Is ON
Synchronization Done
Synchronize
ACPI
PWBTOUT Falling Edge
Resume AND Last State Is OFF
OR
No Resume AND ACPI Is OFF
ON
OFF
PWBTOUT Falling Edge
OR
Software Power Supply Off Command
Figure 4. Legacy Power Supply Control State Diagram
When V_SB is first applied, the PSC state machine is initialized to Power Fail state. In this state, the mechanism waits for the
PC87363 to be initialized according to strap options. Then the PSC enters Check Resume Mode state. In this state, the PSC
checks if Resume to Last PSON state is enabled.
If Resume to Last PSON is enabled, PSON immediately resumes the state it was in when V_SB was lost. To enable this mech-
anism, set bit 2 of the SIOCFD register to 1, and program the ACPI controller to resume OFF state (SLPS3 = 0) after power
fail recovery to allow the PSC to operate properly. If the last state of PSON was OFF, assuming that the ACPI controller also
resumed OFF state, PSON is set to inactive and the PSC enters OFF state. If the last state was ON, under the same as-
sumption, the ACPI controller must be notified to change its state to ON. This is done by pulsing the PWBTOUT output. This
synchronization pulse is generated when the PSC is in Synchronize ACPI state.
If Resume Last PSON State is disabled, the PSC enters either ON or OFF state according to the value of the SLPS3 input,
as follows:
q _{If SLPS3 is low (active, state OFF), the PSC enters OFF state.}
q _{If SLPS3 is high (inactive, state ON), the PSC enters ON state.}
Since SLPS3 reflects the state of the ACPI controller, the PSC actually resumes the current state of the ACPI controller.
After entering either ON or OFF states, PSC moves between these two states on the following conditions:
q _{A falling edge on PWBTOUT (generated internally) changes the state from ON to OFF or vice versa.}
q _{A Software Power Supply Off command, writing 1 to Power Supply Off (bit 1) of the SIOCFD register, changes the}
state from ON to OFF.
Since many wake-up events can activate the PWBTOUT signal, these events can actually cause the PSC to change its state
from OFF to ON, thus activating the PSON output.
As in ACPI mode, the Crowbar protection mechanism is also active in Legacy mode. However, in this mode, when a Crowbar
condition is detected, the PSC returns to OFF state, thus inactivating the PSON output. Also, to synchronize the APCI con-
troller, the PWBTOUT is pulsed to bring it to the correct state.
Table 13 summarizes the bit states that affect PSON V_SB power-up default state.
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