DS90C2501 Datasheet, PDF (7/48 Pages) National Semiconductor (TI) – Transmitter with built-in scaler for LVDS Display Interface (LDI)

Two-Wire Serial Communication Interface Switching Characteristics
Unless otherwise noted, below specifications apply for V_CC3V pin = +3.3V, load capacitance on output lines = 80 pF. Load ca-
pacitance on output lines can be up to 400pF provided that external pull-up is on board. The following parameters are the tim-
ing relationship between SCL and SDA signals related to the DS90C2501.
Symbol
Parameter
Min
Typ
Max
Units
t₁
SCL (Clock) Period
2000
2.5
µs
(Note 7)
t₂
Data in Set-Up Time to SCL High
100
ns
t₃
Data Out Stable after SCL Low
0
ns
t₄
SDA Low Set-Up Time to SCL Low (Start Condition)
100
ns
t₅
SDA High Hold Time after SCL High (Stop Condition)
100
ns
Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the device
should be operated at these limits. The tables of “Electrical Characteristics” specify conditions for device operation.
Note 2: Typical values are given for V_CC = 2.5V and V_CC3V = 3.3V at T_A = +25˚C.
Note 3: Current into device pins is defined as positive. Current out of device pins is defined as negative. Voltages are referenced to ground unless otherwise
specified (except V_OD and ∆V_OD).
Note 4: The limits are based on bench characterization of the device’s jitter response over the power supply voltage range. Output clock jitter is measured with a
cycle-to-cycle jitter of ± 20% data input bit time applied to the input clock signal while data inputs are switching (see figures 11 and 12). This parameter is used when
calculating system margin as described in AN-1059.
Note 5: Receiver Skew Margin is defined as the valid data sampling region at the receiver inputs. This margin takes into account transmitter output pulse positions
(min and max) and the receiver input setup and hold time (internal data sampling window - RSPOS). This margin allows for LVDS interconnect skew, inter-symbol
interference (both dependent on type/length of cable) and clock jitter.
RSKM ≥ cable skew (type, length) + source clock jitter (cycle to cycle).
Note 6: From V = 1.25V of CLKINP to V_DIFF = 0V of CLK1P when EDGE pin = Gnd, DUAL pin = Gnd or V_CC or ¹â„2V_CC , BAL pin= Gnd.
Note 7: Guaranteed by Design
AC Timing Diagrams
FIGURE 1. “Alternate High/Low” Test Pattern in 12-bit Input Mode (Note 8)
20004532
7
www.national.com