DS90C2501 Datasheet, PDF (17/48 Pages) National Semiconductor (TI) – Transmitter with built-in scaler for LVDS Display Interface (LDI)

Serial Bus Protocol (Continued)
FIGURE 12. Byte Read
20004530
The master must generate a “ Start ”, and send the 7-bit
slave address plus a 0 first, and wait for acknowledge from
DS90C2501. When DS90C2501 acknowledges (the 1st
ACK) that the master is calling, the master then sends the
data register address byte, and waits for acknowledge from
the slave. When the slave acknowledges(the 2nd ACK), the
master repeats the “ Start ” by sending the 7-bit slave
address plus a 1 (indicating that READ operation is in
progress), and waits for acknowledge from DS90C2501.
After the slave responds (the 3rd ACK), the slave sends the
data to the bus, and waits for acknowledge from the master.
When the master acknowledges (the 4th ACK), and gener-
ates a “ Stop ”, this completes the “ READ ”.
If the 4th ACK is received from the master and no “ Stop ”
follows it, the slave will keep sending the data of next register
until “ Stop ” is received from the master. If the 4th ACK is not
received from the master, the slave will terminate the Serial
Bus communication, and giving the bus control back to the
master.
FIGURE 13. Byte Write
20004531
The master must generate a “ Start ”, and send the 7-bit
slave address plus a 0 and wait for acknowledge from
DS90C2501. When DS90C2501 acknowledges (the 1st
ACK), that the master is calling, the master then sends the
data register address byte, and waits for acknowledge from
the slave. When the slave acknowledges (the 2nd ACK), the
master sends the data byte and wait for acknowledge from
the slave. When the slave acknowledges (the 3rd ACK), the
master generates a “ Stop ”. This completes the “ WRITE ”.
If the master doesn’t generate the “ Stop ”, the master can
keep sending data to location of the next register address
(Register Address + 1), and waits for acknowledge from the
Host Control Register Descriptions
Register Name: VND_IDL
Address Offset: 00h
Default Value: 05h
Access Method: Read Only
slave. If the slave acknowledges, the master can send data
to the next register address (Register Address + 2). If the
slave doesn’t acknowledges, the master will have the control
of the bus and can generate a “ Stop ” to end the “ WRIT-
E”operation. During the process, if the master attempts to
send data to “ Read Only ” registers, the slave will not
acknowledge and return the bus control back to the master.
A complete programming guide is available for the
DS90C2501 to OEM customers. This can be obtained by
contacting your local National Semiconductor sales
representative.
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