DS90C2501 Datasheet, PDF (15/48 Pages) National Semiconductor (TI) – Transmitter with built-in scaler for LVDS Display Interface (LDI)

DS90C2501 Pin Description (Continued)
Pin Name
Pin No.
I/O Type
Description
OPTION SELECTION
V_REF
83
I-ANALOG This pin is never to be left floating and never tie to GND.
For LVTTL level data input, tie V_REF to V_CC3V. When V_REF > 1.8V, input data
is set to LVTTL level.
For low voltage swing level data input, tie V_REF to ¹â„2V_DDQ (V_DDQ provided by
host interface) V_DDQ is from the host. When V_REF < =1.0V, indicates input
data is in low voltage swing mode.
TST1, TST2,
19, 20, 85
I-LVTTL 2.5
Input data = logic High = V_REF +100 mV in low voltage swing level.
Input data = logic Low = V_REF −100 mV in low voltage swing level.
These pins are used in production testing and should be tied to GND in
TST3
normal operation.
POWER (See Application Information for power supply decoupling requirements)
V_CC/DV_CC
81, 82,
75, 77,
PWR
Power supply pins (pin 75, 77, 81, 82, 96, 119, 123, and 125) for 2.5V LVTTL
inputs and digital circuitry.
96, 119,
123, 125
GND/DGND
33, 73,
PWR
GND or DGND reference for 2.5V TTL inputs and digital circuitry.
74, 76,
78, 79,
80, 84,
118, 122,
124
V_CC3V
121, 127
PWR
The V_CC3V is required for internal logic and certain 3V I/O.
During power up stage, voltage readings on these pins must be higher than
2.5V pins.
GND3V
120, 126,
128
PWR
Ground return pins for V_CC3V powered logic.
SPLLV_CC
SPLLGND
87, 89
86, 88, 90
PWR
PWR
2.5V power supply pins for scaler PLL circuitry. It is not recommended to
share this power with PLLV_CC.
Ground returns for scaler PLL circuitry.
PLLV_CC
PLLGND
92, 94
91, 93, 95
PWR
PWR
2.5V power supply pins for Tx PLL circuitry. It is not recommended to share
this power with SPLLV_CC.
Ground returns for Tx PLL circuitry.
LVDSV_CC
LVDSGND
105, 109
104, 108
PWR
PWR
Power supply pins for LVDS output drivers.
Ground return pins for LVDS output drivers.
LVDSV_CC3V
101, 103,
107, 111
PWR
3V power supply pins for LVDS output drivers.
During power up stage, voltage readings on these pins must be higher than
2.5V pins.
LVDSGND3V 102, 106,
PWR
Ground return pins for 3V LVDS outputs.
110, 112
Note 11: When device power is applied, it is possible for these outputs to switch to a logic “1” momentarily as the 3.3V is rising and before 2.5V reaches at least
0.8V. During this brief period, the pad control logic could be non-deterministic, RESETN will have no effect. It is recommended these outputs are gated externally
if the system design requires them to remain in the inactive logic “0” state during power-on.
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