SC2200 Datasheet, PDF (62/433 Pages) National Semiconductor (TI) – Thin Client On a Chip

Signal Definitions (Continued)
2.4.6 PCI Bus Interface Signals (Continued)
BalL No.
Signal Name
EBGA TEPBGA Type Description
Mux
INTA#
INTB#
INTC#
INTD#
PAR
FRAME#
IRDY#
AE3
D26
I PCI Interrupts. The SC2200 provides inputs
---
for the optional “level-sensitive” PCI inter-
AF1
C26
rupts (also known in industry terms as
---
H4
C9
PIRQx#). These interrupts can be mapped to GPIO19+IOCHRDY
B22
AA2
IRQs of the internal 8259A interrupt control-
lers using PCI Interrupt Steering Registers 1
IDE_DATA7
and 2 (F0 Index 5Ch and 5Dh).
Note: If selected as INTC# or INTD# func-
tion(s) but not used, tie INTC# and
INTD# high.
C10
J4
I/O Parity. Parity generation is required by all
D12
PCI agents. The master drives PAR for
address- and write-data phases. The target
drives PAR for read-data phases. Parity is
even across AD[31:0] and C/BE[3:0]#.
For address phases, PAR is stable and valid
one PCI clock after the address phase. It has
the same timing as AD[31:0] but is delayed
by one PCI clock.
For data phases, PAR is stable and valid one
PCI clock after either IRDY# is asserted on a
write transaction or after TRDY# is asserted
on a read transaction.
Once PAR is valid, it remains valid until one
PCI clock after the completion of the data
phase. (Also see PERR#.)
E1
D8
I/O Frame Cycle. Frame is driven by the current
---
master to indicate the beginning and duration
of an access. FRAME# is asserted to indi-
cate the beginning of a bus transaction.
While FRAME# is asserted, data transfers
continue. FRAME# is deasserted when the
transaction is in the final data phase.
This signal is internally connected to a pull-
up resistor.
C8
F2
I/O Initiator Ready. IRDY# is asserted to indi-
D14
cate that the bus master is able to complete
the current data phase of the transaction.
IRDY# is used in conjunction with TRDY#. A
data phase is completed on any PCI clock in
which both IRDY# and TRDY# are sampled
as asserted. During a write, IRDY# indicates
that valid data is present on AD[31:0]. During
a read, it indicates that the master is pre-
pared to accept data. Wait cycles are
inserted until both IRDY# and TRDY# are
asserted together.
This signal is internally connected to a pull-
up resistor.
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