SC2200 Datasheet, PDF (24/433 Pages) National Semiconductor (TI) – Thin Client On a Chip

Signal Definitions (Continued)
Table 2-2. 432-EBGA Ball Assignment - Sorted by Ball Number (Continued)
Ball
No.
C20²
C21
C22
C23
C24
C25
C26
C27
C28
C29
C30
C31
D1
D2
D3
D4
D5
D6
D7
D8
Signal Name
IDE_DATA9
DDC_SDA
IDE_IOR0#
TFTD10
IDE_DATA6
IRQ9
IDE_DATA3
TFTD12
IDE_DREQ0
TFTD8
IDE_DACK0#
TFTD0
IDE_ADDR1
TFTD2
OVER_CUR#
PLL6B
TEST1
V_IO
X32I
V_PLL3
PCIRST#
GNT1#
DID1
PCICLK0
FPCI_MON
GNT0#
DID0
AD25
D1
AD20
A20
AD18
A18
C/BE2#
D10
I/O Buffer¹ Power
(PU/PD) Type Rail Configuration
I/O
I/O
O
O
I/O
I
I/O
O
I
O
O
O
O
O
I
I/O
O
PWR
IN_TS1,
TS_1/4
IN_T,
OD₄
O_1/4
O_1/4
IN_TS1,
TS_1/4
IN_TS1
IN_TS1,
TS_1/4
O_1/4
IN_TS1
O_1/4
O_1/4
O_1/4
O_1/4
O_1/4
IN_TS
IN_TS,
TS_2/5
O_2/5
---
V_IO PMR[24] = 0
PMR[24] = 1
V_IO PMR[24] = 0
PMR[24] = 1
V_IO PMR[24] = 0
PMR[24] = 1
V_IO PMR[24] = 0
PMR[24] = 1
V_IO PMR[24] = 0
PMR[24] = 1
V_IO PMR[24] = 0
PMR[24] = 1
V_IO PMR[24] = 0
PMR[24] = 1
V_IO ---
V_IO PMR[29] = 0
PMR[29] = 1
--- ---
I
PWR
WIRE
---
V_BAT ---
--- ---
O
O_PCI
O
O_PCI
I
IN_STRP
(PD₁₀₀)
O
O_PCI
I
IN_STRP
(PD₁₀₀)
O
O_PCI
I
IN_STRP
(PD₁₀₀)
I/O IN_PCI,
O_PCI
I/O IN_PCI,
O_PCI
I/O IN_PCI,
O_PCI
O
O_PCI
I/O IN_PCI,
O_PCI
O
O_PCI
I/O IN_PCI,
(PU_22.5) _OPCI
I/O IN_PCI,
(PU_22.5) _OPCI
V_IO ---
V_IO ---
Strap (See Table 2-
6 on page 51.)
V_IO ---
Strap (See Table 2-
6 on page 51.)
V_IO ---
Strap (See Table 2-
6 on page 51.)
V_IO Cycle Multiplexed
V_IO Cycle Multiplexed
V_IO Cycle Multiplexed
V_IO Cycle Multiplexed
Ball
No. Signal Name
D9
STOP#
D15
D10
D11
D12
D13
D14
D15
D16
V_SS
V_CORE
V_SS
V_CORE
V_SS
V_CORE
AD1
D17
D18
D19
D20
D21
D22
D23
A1
V_CORE
V_SS
V_CORE
V_SS
V_CORE
V_SS
IDE_DATA2
TFTD14
D24 IDE_IOW0#
TFTD9
D25 IRQ14
TFTD1
D26 SIN1
D27 X27O
D28 PLL2B
TEST0
D29 X32O
D30
V_BAT
D31 LED#
E1
FRAME#
E2
PCICLK
E3
REQ1#
E4
PCICLK1
LPC_ROM
E28
AV_SSPLL3
E29 PWRBTN#
E30^{4, 5 ONCTL#}
E31 GPWIO0
I/O Buffer¹ Power
(PU/PD) Type Rail Configuration
I/O IN_PCI,
(PU_22.5) _OPCI
I/O IN_PCI,
(PU_22.5) _OPCI
GND ---
V_IO Cycle Multiplexed
--- ---
PWR ---
--- ---
GND ---
--- ---
PWR ---
--- ---
GND ---
--- ---
PWR ---
--- ---
I/O
O
PWR
IN_PCI,
O_PCI
O_PCI
---
V_IO Cycle Multiplexed
--- ---
GND ---
--- ---
PWR ---
--- ---
GND ---
--- ---
PWR ---
--- ---
GND ---
--- ---
I/O
O
O
O
I
O
I
O
I/O
O
O
PWR
IN_TS1,
TS_1/4
O_1/4
O_1/4
O_1/4
IN_TS1
O_1/4
IN_TS
WIRE
IN_T,
TS_2/5
O_2/5
WIRE
---
V_IO PMR[24] = 0
PMR[24] = 1
V_IO PMR[24] = 0
PMR[24] = 1
V_IO PMR[24] = 0
PMR[24] = 1
V_IO ---
V_IO ---
V_IO PMR[29] = 0
PMR[29] = 1
V_BAT ---
--- ---
O
OD₁₄
I/O IN_PCI,
(PU_22.5) _OPCI
I
IN_T
I
IN_PCI
(PU_22.5)
O
O_PCI
I
IN_STRP
(PD₁₀₀₎
GND ---
V_SB ---
V_IO ---
V_IO ---
V_IO ---
V_IO ---
Strap (See Table 2-
6 on page 51.)
--- ---
I
IN_BTN
(PU₁₀₀₎
O
OD₁₄
I/O
IN_TS,
(PU₁₀₀) _TS2/14
V_SB ---
V_SB ---
V_SB ---
www.national.com
24
Revision 3.0