SC2200 Datasheet, PDF (210/433 Pages) National Semiconductor (TI) – Thin Client On a Chip

Core Logic Module (Continued)
Table 5-29. F0: PCI Header and Bridge Configuration Registers for GPIO and LPC Support (Continued)
Bit Description
Index 76h
IOCS0# Control Register (R/W)
This register is used in conjunction with F0 Index 74h (IOCS0# Base Address register).
Reset Value: 00h
7
I/O Chip Select 0 Positive Decode (IOCS0#).
0: Disable.
1: Enable.
6
Writes Result in Chip Select. When this bit is set to 1, writes to configured I/O address (base address configured in F0
Index 74h; range configured in bits [4:0]) cause IOCS0# to be asserted.
0: Disable.
1: Enable.
5
Reads Result in Chip Select. When this bit is set to 1, reads from configured I/O address (base address configured in F0
Index 74h; range configured in bits [4:0]) cause IOCS0# to be asserted.
0: Disable.
1: Enable.
4:0 IOCS0# I/O Address Range. This 5-bit field is used to select the range of IOCS0#.
00000: 1 Byte
00001: 2 Bytes
00011: 4 Bytes
00111: 8 Bytes
01111: 16 Bytes
11111: 32 Bytes
All other combinations are reserved.
Index 77h
Reserved
Reset Value: 00h
Index 78h-7Bh
DOCCS# Base Address Register (R/W)
Reset Value: 00000000h
31:0
DiskOnChip Chip Select Base Address. This 32-bit value represents the memory base address used to enable assertion
of DOCCS# (EBGA ball H3 or AJ13 / TEPBGA ball A9 or N31, see PMR[23] in Table 3-2 on page 81).
This register is used in conjunction with F0 Index 7Ch (DOCCS# Control register).
Index 7Ch-7Fh
DOCCS# Control Register (R/W)
This register is used in conjunction with F0 Index 78h (DOCCS# Base Address register).
Reset Value: 00000000h
31:27
26
25
24
23:19
18:0
Reserved. Must be set to 0.
DiskOnChip Chip Select Positive Decode (DOCCS#).
0: Disable.
1: Enable.
Writes Result in Chip Select. When this bit is set to 1, writes to configured memory address (base address configured in
F0 Index 78h; range configured in bits [18:0]) cause DOCCS# to be asserted.
0: Disable.
1: Enable.
Reads Result in Chip Select. When this bit is set to 1, reads from configured memory address (base address configured in
F0 Index 78h; range configured in bits [18:0]) cause DOCCS# to be asserted.
0: Disable.
1: Enable.
Reserved. Must be set to 0.
DOCCS# Memory Address Range. This 19-bit mask is used to qualify accesses on which DOCCS# is asserted by mask-
ing the upper 19 bits of the incoming PCI address (AD[31:13]).
Index 80h
Power Management Enable Register 1 (R/W)
Reset Value: 00h
7:6 Reserved. Must be set to 0.
5
Codec SDATA_IN SMI. When set to 1, this bit allows an SMI to be generated in response to an AC97 codec producing a
positive edge on SDATA_IN.
0: Disable.
1: Enable.
Top level SMI status is reported at F1BAR0+I/O Offset 00h/02h[0].
Second level SMI status is reported at F0 Index 87h/F7h[2].
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