SC2200 Datasheet, PDF (303/433 Pages) National Semiconductor (TI) – Thin Client On a Chip

Core Logic Module (Continued)
Table 5-43. DMA Channel Control Registers (Continued)
Bit Description
I/O Port 00Bh
DMA Channel Mode Register, Channels 3:0 (WO)
7:6 Transfer Mode.
00: Demand.
01: Single.
10: Block.
11: Cascade.
5
Address Direction.
0: Increment.
1: Decrement.
4
Auto-initialize.
0: Disable.
1: Enable.
3:2 Transfer Type.
00: Verify.
01: Memory read.
10: Memory write.
11:
Reserved.
1:0 Channel Number Mode Select.
00: Channel 0.
01: Channel 1.
10: Channel 2.
11: Channel 3.
I/O Port 00Ch
DMA Clear Byte Pointer Command, Channels 3:0 (W)
I/O Port 00Dh
DMA Master Clear Command, Channels 3:0 (W)
I/O Port 00Eh
DMA Clear Mask Register Command, Channels 3:0 (W)
I/O Port 00Fh
DMA Write Mask Register Command, Channels 3:0 (W)
I/O Port 0C0h
Not used.
DMA Channel 4 Address Register (R/W)
I/O Port 0C2h
Not used.
DMA Channel 4 Transfer Count Register (R/W)
I/O Port 0C4h
Memory address bytes 1 and 0.
DMA Channel 5 Address Register (R/W)
I/O Port 0C6h
Transfer count bytes 1 and 0.
DMA Channel 5 Transfer Count Register (R/W)
I/O Port 0C8h
Memory address bytes 1 and 0.
DMA Channel 6 Address Register (R/W)
I/O Port 0CAh
Transfer count bytes 1 and 0.
DMA Channel 6 Transfer Count Register (R/W)
I/O Port 0CCh
Memory address bytes 1 and 0.
DMA Channel 7 Address Register (R/W)
I/O Port 0CEh
Transfer count bytes 1 and 0.
DMA Channel 7 Transfer Count Register (R/W)
Revision 3.0
303
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