SC2200 Datasheet, PDF (39/433 Pages) National Semiconductor (TI) – Thin Client On a Chip

Signal Definitions (Continued)
Table 2-4. 481-TEPBGA Ball Assignment - Sorted by Ball Number (Continued)
Ball
No. Signal Name
C16
AV_SSPLL2
C17^{6,2 SLCT}
TFTD15
F_C/BE3#
C18 PD4
TFTD10
F_AD4
C19^{6,2 PD5}
TFTD11
F_AD5
C20^{6,2 PD3}
TFTD9
F_AD3
C21^{6,2 PD0}
TFTD6
F_AD0
C22 V_IO
C23 NC
C24 NC
C25 V_IO
C26 INTB#
C27
AV_SSUSB
C28 GPIO9
DCD2#
IDE_IOW1#
SDTEST2
I/O Buffer¹ Power
(PU/PD) Type Rail Configuration
GND ---
--- ---
I
IN_T
O
O_1/4
O
O_1/4
I/O
IN_T,
O_14/14
O
O_1/4
O
O_14/14
I/O
IN_T,
O_14/14
O
O_1/4
O
O_14/14
I/O
IN_T,
O_14/14
O
O_1/4
O
O_14/14
I/O
IN_T,
O_14/14
O
O_1/4
O
O_14/14
PWR ---
V_{IO PMR[23]}3 _{= 0 and}
(PMR[27] = 0 and
FPCI_MON = 0)
PMR[23]³ = 1 and
(PMR[27] = 0 and
FPCI_MON = 0)
PMR[23]³ = 0 and
(PMR[27] = 1 or
FPCI_MON = 1)
V_{IO PMR[23]}3 _{= 0 and}
(PMR[27] = 0 and
FPCI_MON = 0)
PMR[23]³ = 1 and
(PMR[27] = 0 and
FPCI_MON = 0)
PMR[23]³ = 0 and
(PMR[27] = 1 or
FPCI_MON = 1)
V_{IO PMR[23]}3 _{= 0 and}
(PMR[27] = 0 and
FPCI_MON = 0)
PMR[23]³ = 1 and
(PMR[27] = 0 and
FPCI_MON = 0)
PMR[23]³ = 0 and
(PMR[27] = 1 or
FPCI_MON = 1)
V_{IO PMR[23]}3 _{= 0 and}
(PMR[27] = 0 and
FPCI_MON = 0)
PMR[23]³ = 1 and
(PMR[27] = 0 and
FPCI_MON = 0)
PMR[23]³ = 0 and
(PMR[27] = 1 or
FPCI_MON = 1)
V_{IO PMR[23]}3 _{= 0 and}
(PMR[27] = 0 and
FPCI_MON = 0)
PMR[23]³ = 1 and
(PMR[27] = 0 and
FPCI_MON = 0)
PMR[23]³ = 0 and
(PMR[27] = 1 or
FPCI_MON = 1)
--- ---
---
---
---
---
PWR ---
--- ---
--- ---
--- ---
I
(PU_22.5)
GND
IN_PCI
---
V_IO ---
--- ---
I/O
(PU_22.5)
I
(PU_22.5)
O
(PU_22.5)
O
(PU_22.5)
IN_TS,
O_1/4
IN_TS
O_1/4
O_2/5
V_IO PMR[18] = 0 and
PMR[8] = 0
PMR[18] = 1 and
PMR[8] = 0
PMR[18] = 0 and
PMR[8] = 1
PMR[18] = 1 and
PMR[8] = 1
Ball
I/O Buffer¹ Power
No. Signal Name (PU/PD) Type Rail Configuration
C29 V_IO
PWR ---
--- ---
C30 GPIO7
I/O
IN_TS,
(PU_22.5) _O1/4
V_IO PMR[17] = 0 and
PMR[8] = 0
RTS2#
O
O_1/4
(PU_22.5)
PMR[17] = 1 and
PMR[8] = 0
IDE_DACK1#
O
O_1/4
(PU_22.5)
PMR[17] = 0 and
PMR[8] = 1
SDTEST0
O
O_2/5
(PU_22.5)
PMR[17] = 1 and
PMR[8] = 1
C31 GPIO8
I/O
IN_TS,
(PU_22.5) _O8/8
V_IO PMR[17] = 0 and
PMR[8] = 0
CTS2#
I
IN_TS
(PU_22.5)
PMR[17] = 1 and
PMR[8] = 0
IDE_DREQ1
I
IN_TS1
(PU_22.5)
PMR[17] = 0 and
PMR[8] = 1
SDTEST4
O
O_2/5
(PU_22.5)
PMR[17] = 1 and
PMR[8] = 1
D1
AD21
I/O IN_PCI, V_IO Cycle Multiplexed
O_PCI
A21
O
O_PCI
D2
AD22
I/O IN_PCI, V_IO Cycle Multiplexed
O_PCI
A22
O
O_PCI
D3
AD20
I/O IN_PCI, V_IO Cycle Multiplexed
O_PCI
A20
O
O_PCI
D4
AD27
I/O IN_PCI, V_IO Cycle Multiplexed
O_PCI
D3
I/O IN_PCI,
O_PCI
D5
AD31
I/O IN_PCI, V_IO Cycle Multiplexed
O_PCI
D7
I/O IN_PCI,
O_PCI
D6
PCICLK1
O
O_PCI
V_IO ---
LPC_ROM
I
IN_STRP
(PD₁₀₀)
Strap (See Table 2-
6 on page 51.)
D7
V_SS
GND ---
--- ---
D8
FRAME#
I/O IN_PCI,
(PU_22.5) _OPCI
V_IO ---
D9
IOR#
O
O_3/5
V_IO PMR[21] = 0 and
PMR[2] = 0
DOCR#
O
O_3/5
PMR[21] = 0 and
PMR[2] = 1
GPIO14
I/O
IN_TS,
(PU_22.5) _O3/5
PMR[21] = 1 and
PMR[2] = 1
D10 GPIO1
I/O
IN_T,
(PU_22.5) _O3/5
V_{IO PMR[23]}3 _{= 0 and}
PMR[13] = 0
IOCS1#
O
O_3/5
(PU_22.5)
V_{IO PMR[23]}3 _{= 0 and}
PMR[13] = 1
TFTD12
O
O_1/4
(PU_22.5)
V_{IO PMR[23]}3 _{= 1}
D11 TRDE#
O
O_3/5
V_IO PMR[12] = 0
GPIO0
I/O
IN_TS,
(PU_22.5) _O3/5
V_IO PMR[12] = 1
D12
V_CCCRT
PWR ---
--- ---
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