DS92LV0421 Datasheet, PDF (6/40 Pages) National Semiconductor (TI) – 10 - 75 MHz Channel Link II Serializer/Deserializer with LVDS Parallel Interface

Pin Name
Pin #
I/O, Type Description
LVCMOS Outputs
LOCK
27
O, LVCMOS LOCK Status Output
LOCK = 1, PLL is locked, output stated determined by OEN.
LOCK = 0, PLL is unlocked, output states determined by OSS_SEL and OEN.
See Table 5.
Control and Configuration
PDB
1
I, LVCMOS Power-down Mode Input
w/ pull-down PDB = 1, Device is enabled (normal operation).
Refer to ”Power Up Requirements and PDB Pin” in the Applications Information Section.
PDB = 0, Device is powered down
When the Device is in the power-down state, the driver outputs (DOUT+/-) are both logic
high, the PLL is shutdown, IDD is minimized. Control Registers are RESET.
VODSEL
33
I, LVCMOS Parallel LVDS Driver Output Voltage Select — Pin or Register Control
w/ pull-down VODSEL = 1, LVDS VOD is ±450 mV, 900 mVp-p (typ) — Long Cable / De-E Applications
VODSEL = 0, LVDS VOD is ±300 mV, 600 mVp-p (typ)
OEN
30
I, LVCMOS Output Enable.
w/ pull-down See Table 5.
OSS_SEL
35
I, LVCMOS Output Sleep State Select Input.
w/ pull-down See Table 5.
LFMODE
36
I, LVCMOS SSCG Low Frequency Mode — Pin or Register Control
w/ pull-down LF_MODE = 1, low frequency mode (TxCLKOUT = 10–20 MHz)
LF_MODE = 0, high frequency mode (TxCLKOUT = 20–65 MHz)
SSCG not avaialble above 65 MHz.
MAPSEL
34
I, LVCMOS Channel Link Map Select — Pin or Register Control
w/ pull-down MAPSEL = 1, MSB on TxOUT3+/-.
MAPSEL = 0, LSB on TxOUT3+/-.
CONFIG
[1:0]
11, 10
I, LVCMOS Operating Modes — Pin or Limited Register Control
w/ pull-down Determine the device operating mode and interfacing device.
CONFIG[1:0] = 00: Interfacing to DS92LV2421 or DS92LV0421, Control Signal Filter
DISABLED
CONFIG[1:0] = 01: Interfacing to DS92LV2421 or DS92LV0421, Control Signal Filter
ENABLED
CONFIG [1:0] = 10: Interfacing to DS90UR241, DS99R421
CONFIG [1:0] = 11: Interfacing to DS90C124
SSC[2:0]
7, 2, 3
I, LVCMOS Spread Spectrum Clock Generation (SSCG) Range Select
w/ pull-down See Table 8 Table 9
RES
37
I, LVCMOS Reserved
w/ pull-down
Control and Configuration — STRAP PIN
EQ
28 [PASS]
STRAP EQ Gain Control of Channel Link II Serial Input
I, LVCMOS EQ = 1, EQ gain is enabled (~13 dB)
w/ pull-down EQ = 0, EQ gain is disabled (~1.625 dB)
Optional BIST Mode
BISTEN
29
I, LVCMOS BIST Mode — Optional
w/ pull-down BISTEN = 1, BIST is enabled
BISTEN = 0, BIST is disabled
PASS
28
O, LVCMOS
PASS Output (BIST Mode) — Optional
PASS =1, no errors detected
PASS = 0, errors detected
Leave open if unused. Route to a test point (pad) recommended.
www.national.com
6