DS92LV0421 Datasheet, PDF (12/40 Pages) National Semiconductor (TI) – 10 - 75 MHz Channel Link II Serializer/Deserializer with LVDS Parallel Interface

Symbol
Parameter
Conditions
t_HLT
Output High-to-Low Transition R_L = 100Ω, De-emphasis = disabled,
Time
VODSEL = 0
Figure 4
R_L = 100Ω, De-emphasis = disabled,
VODSEL = 1
t_XZD
Ouput Active to OFF Delay,
Figure 9
t_PLD
PLL Lock Time, Figure 7
t_SD
Delay - Latency, Figure 10
t_DJIT
Output Total Jitter,
Figure 12
R_L = 100Ω
R_L = 100Ω
R_L = 100Ω, De-Emph = disabled,
RANDOM pattern
λ_STXBW Jitter Transfer
Function -3 dB Bandwidth
δ_STX
Jitter Transfer
Function Peaking
DS92LV0422 CHANNEL LINK II CML INPUT
t_DDLT Lock Time
SSCG = OFF,
10 MHz
SSCG = ON,
10 MHz
SSCG = OFF,
75 MHz
SSCG = ON,
75 MHz
t_DJIT
Input Jitter Tolerance
EQ = OFF
Jitter Frequency > 10 MHz
DS92LV0422 LVCMOS OUTPUTS
t_CLH
Low to High Transition Time C_L = 8 pF
t_CHL
High to Low Transition Time ^{LOCK pin,}
PASS pin
t_PASS
BIST PASS Valid Time,
BISTEN = 1
PASS pin
10 MHz
75 MHz
DS92LV0422 SSCG MODE
t_DEV
Spread Spectrum Clocking
TxCLKOUT = 10 – 65 MHz,
Deviation Frequency
SSC[2:0] = ON
t_MOD Spread Spectrum Clocking
Modulation Frequency
TxCLKOUT = 10 – 65 MHz,
SSC[2:0] = ON
Min Typ Max Units
130
260 390
ps
100
200 300
ps
TBD TBD ns
10
ms
140*T TBD ns
0.3 TBD UI
TBD
kHz
TBD
dB
TBD
ms
TBD
ms
TBD
ms
TBD
ms
>0.45
UI
10
15
ns
10
15
ns
560 570
ns
70
75
ns
±0.5
±2
%
8
100 kHz
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