DS92LV0421 Datasheet, PDF (34/40 Pages) National Semiconductor (TI) – 10 - 75 MHz Channel Link II Serializer/Deserializer with LVDS Parallel Interface

DS92LV0422 TYPICAL APPLICATION CONNECTION
shows a typical application of the DS92LV0422 for a 75 MHz
24-bit Color Display Application. The CML inputs require 0.1
μF AC coupling capacitors to the line. The line driver includes
internal termination. Bypass capacitors are placed near the
power supply pins. At a minimum, four 0.1 µF capacitors and
a 4.7 µF capacitor should be used for local device bypassing.
System GPO (General Purpose Output) signals control the
PDB and BISTEN pins. The application assumes the com-
panion deserializer (DS92LV0422) therefore the configura-
tion pins are also both tied Low. . The interface to the host is
with 1.8 V LVCMOS levels, thus the VDDIO pin is connected
also to the 1.8V rail. The Optional Serial Bus Control is not
used in this example, thus the SCL, SDA and ID[x] pins are
left open. A delay cap is placed on the PDB signal to delay
the enabling of the device until power is stable. Bypass ca-
pacitors are placed near the power supply pins. Ferrite beads
are placed on the power lines for effective noise suppression.
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FIGURE 32. DS92LV0422 Typical Connection Diagram
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