DS92LV0421 Datasheet, PDF (37/40 Pages) National Semiconductor (TI) – 10 - 75 MHz Channel Link II Serializer/Deserializer with LVDS Parallel Interface

ing noise effects between different sections of the circuit.
Separate planes on the PCB are typically not required. Pin
Description tables typically provide guidance on which circuit
blocks are connected to which power pin pairs. In some cas-
es, an external filter many be used to provide clean power to
sensitive circuits such as PLLs.
Use at least a four layer board with a power and ground plane.
Locate LVCMOS signals away from the LVDS lines to prevent
coupling from the LVCMOS lines to the LVDS lines. Closely-
coupled differential lines of 100 Ohms are typically recom-
mended for LVDS interconnect. The closely coupled lines
help to ensure that coupled noise will appear as common-
mode and thus is rejected by the receivers. The tightly cou-
pled lines will also radiate less.
Information on the LLP style package is provided in National
Application Note: AN-1187.
LVDS INTERCONNECT GUIDELINES
See AN-1108 and AN-905 for full details.
• Use 100Ω coupled differential pairs
• Use the S/2S/3S rule in spacings
– S = space between the pair
– 2S = space between pairs
– 3S = space to LVCMOS signal
• Minimize the number of Vias
• Use differential connectors when operating above
500Mbps line speed
• Maintain balance of the traces
• Minimize skew within the pair
• Terminate as close to the TX outputs and RX inputs as
possible
Additional general guidance can be found in the LVDS
Owner’s Manual - available in PDF format from the National
web site at: www.national.com/lvds
37
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