DS92LV0421 Datasheet, PDF (24/40 Pages) National Semiconductor (TI) – 10 - 75 MHz Channel Link II Serializer/Deserializer with LVDS Parallel Interface

Optional Serial Bus Control
Please see the following section on the optional Serial Bus
Control Interface.
Optional BIST Mode
Please see the following section on the chipset BIST mode
for details.
DESERIALIZER Functional
Description
The Des converts a single input serial data stream to a wide
parallel output bus, and also provides a signal check for the
chipset Built In Self Test (BIST) mode. The device can be
configured via external pins and strap pins or through the op-
tional serial control bus. The Des features enhance signal
quality on the link with an integrated equalizer on the serial
input and Channel Link II data encoding which provides ran-
domization, scrambling, and DC balanacing of the data. The
Des includes multiple features to reduce EMI associated with
data transmission. This includes the randomization and
scrambling of the data, the output spread spectrum clock
generation (SSCG) support and output clock and data slew
rate select. The Des features power saving features with a
power down mode, and optional LVCMOS (1.8 V) interface
compatibility.
TABLE 5. Des Output State Table
Oscillator Output — Optional
The DS92LV0422 provides an optional TxCLKOUT when the
input clock (serial stream) has been lost. This is based on an
internal oscillator. The frequency of the oscillator may be se-
lected. This feature may be controlled by the external pin or
through the registers.
CLOCK-DATA RECOVERY STATUS FLAC (LOCK),
OUTPUT ENABLE (OEN) AND OUTPUT STATE SELECT
()SS_SEL)
When PDB is driven HIGH, the CDR PLL begins locking to
the serial input, LOCK is LOW and the Channel Link interface
state is determined by the state of the OSS_SEL pin.
After the DS92LV0422 completes its lock sequence to the in-
put serial data, the LOCK output is driven HIGH, indicating
valid data and clock recovered from the serial input is avail-
able on the Channel Link outputs. The TxCLKOUT output is
held at its current state at the change from OSC_CLK (if this
is enabled via OSC_SEL) to the recovered clock (or vice ver-
sa). Note that the Channel Link outputs may be held in an
inactive state (TRI-STATE®) through the use of the Output
Enable pin (OEN).
If there is a loss of clock from the input serial stream, LOCK
is driven LOW and the state of the outputs are based on the
OSS_SEL setting (configuration pin or register).
INPUTS
PDB OEN
L
X
OSS_SEL
X
L
X
L
H
L
H
H
H
H
H
L
X
H
H
X
OUTPUTS
LOCK OTHER OUTPUTS
X
TxCLKOUT is TRI-STATE®
TxOUT[3:0] are TRI-STATE®
PASS is TRI-STATE®
L
TxCLKOUT is TRI-STATE®
TxOUT[3:0] are TRI-STATE®
PASS is HIGH
L
TxCLKOUT is TRI-STATE®
TxOUT[3:0] are TRI-STATE®
PASS is TRI-STATE®
L
TxCLKOUT is TRI-STATE® or OSC Output through Register bit
TxOUT[3:0] are TRI-STATE®
PASS is TRI-STATE®
H
TxCLKOUT is TRI-STATE®
TxOUT[3:0] are TRI-STATE®
PASS is HIGH
H
TxCLKOUT is Active
TxOUT[3:0] are Active
PASS is Active
(Normal operating mode)
Des — Integrated Signal Conditioning Features — Des
Des — Common Mode Filter Pin (CMF) — Optional
The Des provides access to the center tap of the internal ter-
mination. A capacitor may be placed on this pin for additional
common-mode filtering of the differential pair. This can be
useful in high noise environments for additional noise rejec-
tion capability. A 0.1μF capacitor may be connected to this
pin to Ground.
Des — Input Equalizer Gain (EQ)
The Des can enable receiver input equalization of the serial
stream to increase the eye opening to the Des input. Note this
function cannot be seen at the RxIN+/- input. The equalization
feature may be controlled by the external pin or by register.
TABLE 6. Receiver Equalization
Configuration Table
EQ (Strap Option)
Effect
L
OFF, ~1.625 dB
H
~13 dB
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