DS92LV0421 Datasheet, PDF (23/40 Pages) National Semiconductor (TI) – 10 - 75 MHz Channel Link II Serializer/Deserializer with LVDS Parallel Interface

SERIALIZER Functional Description
The Ser converts a Channel Link LVDS clock and data bus to
a single serial output data stream, and also acts as a signal
generator for the chipset Built In Self Test (BIST) mode. The
device can be configured via external pins or through the op-
tional serial control bus. The Ser features enhanced signal
quality on the link by supporting: a selectable VOD level, a
selectable de-emphasis signal conditioning and also the
Channel Link II data coding that provides randomization,
scrambling, and DC Balanacing of the data. The Ser includes
multiple features to reduce EMI associated with display data
transmission. This includes the randomization and scram-
bling of the serial data and also the system spread spectrum
clock support. The Ser features power saving features with a
sleep mode, auto stop clock feature, and optional 1.8 V or
3.3V I/O compatibility.
See also the Functional Description of the chipset's serial
control bus and BIST modes.
EMI Reduction Features
Data Randomization & Scrambling
Channel Link II Ser / Des feature a 3 step encoding process
which enables the use of AC coupled interconnects and also
helps to manage EMI. The serializer first passes the parallel
data through a scrambler which randomizes the data. The
randomized data is then DC balanced. The DC balanced and
randomized data then goes through a bit shuffling circuit and
is transmitted out on the serial line. This encoding process
helps to prevent static data patterns on the serial stream. The
resulting frequency content of the serial stream ranges from
the parallel clock frequency to the nyquist rate. For example,
if the Ser / Des chip set is operating at a parallel clock fre-
quency of 50 MHz, the resulting frequency content of serial
stream ranges from 50 MHz to 700 MHz ( 50 MHz *28 bits =
1.4 Gbps / 2 = 700 MHz ).
Ser — Spread Spectrum Compatibility
The RxCLKIN of the Channel Link input is capable of tracking
spread spectrum clocking (SSC) from a host source. The Rx-
CLKIN will accept spread spectrum tracking up to 35kHz
modulation and ±0.5, ±1 or ±2% deviations (center spread).
The maximum conditions for the RxCLKIN input are: a mod-
ulation frequency of 35kHz and amplitude deviations of ±2%
(4% total).
Ser — Integrated Signal Conditioning Features
Ser — VOD Select (VODSEL)
The DS92LV0421 differential output voltage may be in-
creased by setting the VODSEL pin High. When VODSEL is
Low, the DC VOD is at the standard (default) level. When
VODSEL is High, the DC VOD is increased in level. The in-
creased VOD is useful in extremely high noise environments
and also on extra long cable length applications. When using
de-emphasis it is recommended to set VODSEL = H to avoid
excessive signal attenuation especially with the larger de-
emphasis settings. This feature may be controlled by the
external pin or by register.
TABLE 3. Ser — Differential Output Voltage
Input
Effect
VODSEL
VOD
mV
VOD
mVp-p
H
±420
840
L
±280
560
Ser — De-Emphasis (De-Emph)
The De-Emph pin controls the amount of de-emphasis be-
ginning one full bit time after a logic transition that the device
drives. This is useful to counteract loading effects of long or
lossy cables. This pin should be left open for standard switch-
ing currents (no de-emphasis) or if controlled by register. De-
emphasis is selected by connecting a resistor on this pin to
ground, with R value between 0.5 kΩ to 1 MΩ, or by register
setting. When using De-Emphasis it is recommended to set
VODSEL = H.
TABLE 4. De-Emphasis Resistor Value
Resistor Value (kΩ)
De-Emphasis Setting
Open
Disabled
0.6
- 12 dB
1.0
- 9 dB
2.0
- 6 dB
5.0
- 3 dB
30120960
FIGURE 23. De-Emph vs. R value
Power Saving Features
Ser — Power Down Feature (PDB)
The DS92LV0421 has a PDB input pin to ENABLE or POWER
DOWN the device. This pin is controlled by the host and is
used to save power, disabling the link when the display is not
needed. In the POWER DOWN mode, the high-speed driver
outputs are both pulled to VDD and present a 0V VOD state.
Note – in POWER DOWN, the optional Serial Bus Control
Registers are RESET.
Ser — Stop Clock Feature
The DS92LV0421 will enter a low power SLEEP state when
the RxCLKIN is stopped. A STOP condition is detected when
the input clock frequency is less than 3 MHz. The clock should
be held at a static Low or high state. When the RxCLKIN starts
again, the device will then lock to the valid input RxCLKIN and
then transmits the RGB data to the desializer. Note – in STOP
CLOCK SLEEP, the optional Serial Bus Control Registers
values are RETAINED.
1.8V or 3.3V VDDIO Operation
The DS92LV0421 parallel control bus can operate with 1.8 V
or 3.3 V levels (V_DDIO) for host compatibility. The 1.8 V levels
will offer a system power savings.
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