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DS92LV0421 Datasheet, PDF (11/40 Pages) National Semiconductor (TI) – 10 - 75 MHz Channel Link II Serializer/Deserializer with LVDS Parallel Interface
◁
Symbol
IDDZ
IDDTXZ
IDDIOZ
Parameter
Supply Current Power Down
Conditions
Pin/Freq.
PDB = 0V,
All other LVCMOS
Inputs = 0V
VDD = 1.89 V All VDD(1:8)
pins
VDDTX = 3.6 V VDDTX
VDDIO = 1.89 VDDIO
V
VDDIO = 3.6V
Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
DS92LV0421 CHANNEL LINK PARALLEL LVDS INPUT
tRSP0
tRSP1
tRSP2
tRSP3
tRSP4
tRSP5
tRSP6
RJIT
Receiver Strobe Position-bit 0
Receiver Strobe Position-bit 1
Receiver Strobe Position-bit 2
Receiver Strobe Position-bit 3
Receiver Strobe Position-bit 4
RxCLKIN = 75 MHz,
RxIN[3:0]
Figure 5
Receiver Strobe Position-bit 5
Receiver Strobe Position-bit 6
RxCLKIN Cycle-to-Cycle Jitter
(Input clock requirement)
DS92LV0422 CHANNEL LINK PARALLEL LVDS OUTPUT
tLHT
tTHLT
tDCCJ
Low to High Transition Time
High to Low Transition Time
Cycle-to-Cycle Output Jitter
RL = 100Ω
TxCLKOUT± = 10 MHz
TxCLKOUT± = 75MHz
tTTP1
Transmitter Pulse Position for 10 – 75 MHz
bit 1
tTTP0
Transmitter Pulse Position for
bit 0
tTTP6
Transmitter Pulse Position for
bit 6
tTTP5
Transmitter Pulse Position for
bit 5
tTTP4
Transmitter Pulse Position for
bit 4
tTTP3
Transmitter Pulse Position for
bit 3
tTTP2
Transmitter Pulse Position for
bit 2
tSD
tTPDD
Delay-Latency
Power Down Delay
Active to OFF
75 MHz
tTXZR
Enable Delay
OFF to Active
75 MHz
DS92LV0421 Channel Link II CML OUTPUT
tHLT
Output Low-to-High Transition RL = 100Ω, De-emphasis = disabled,
Time
VODSEL = 0
Figure 3
RL = 100Ω, De-emphasis = disabled,
VODSEL = 1
Min
Min
TBD
TBD
TBD
TBD
TBD
TBD
TBD
100
100
Typ
TBD
Max Units
TBD mA
TBD TBD mA
TBD TBD mA
TBD TBD mA
Typ Max Units
1.1 TBD ns
3.3 TBD ns
5.5 TBD ns
7.7 TBD ns
9.9 TBD ns
12.1 TBD ns
14.3 TBD ns
TBD ns
0.3
0.6
ns
0.3
0.6
ns
900 2100 ps
75
125
ps
0
UI
1
UI
2
UI
3
UI
4
UI
5
UI
6
UI
TBD TBD ns
6
10
ns
40
55
ns
200
300
ps
200
300
ps
11
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