DS92LV0421 Datasheet, PDF (27/40 Pages) National Semiconductor (TI) – 10 - 75 MHz Channel Link II Serializer/Deserializer with LVDS Parallel Interface

Built In Self Test (BIST)
An optional At-Speed Built In Self Test (BIST) feature sup-
ports the testing of the high-speed serial link. This is useful in
the prototype stage, equipment production, in-system test
and also for system diagnostics. In the BIST mode only a input
clock is required along with control to the Ser and Des BIS-
TEN input pins. The Ser outputs a test pattern (PRBS7) and
drives the link at speed. The Des detects the PRBS7 pattern
and monitors it for errors. A PASS output pin toggles to flag
any payloads that are received with 1 to 24 errors. Upon com-
pletion of the test, the result of the test is held on the PASS
output until reset (new BIST test or Power Down). A high on
PASS indicates NO ERRORS were detected. A Low on PASS
indicates one or more errors were detected. The duration of
the test is controlled by the pulse width applied to the Des
BISTEN pin.
Inter-operability is supported between this Channel Link II de-
vice and all Channel Link II generations (Gen 1/2/3) — see
respective datasheets for details on entering BIST mode and
control.
Sample BIST Sequence
See Figure 25 for the BIST mode flow diagram.
Step 1: Place the serializer in BIST Mode by setting Ser BIS-
TEN = H. The BIST Mode is enabled via the BISTEN pin. An
RxCLKIN is required for all the Ser options. When the dese-
rializer detects the BIST mode pattern and command the
parallel data and control signal outputs are shut off.
Step 2: Place the deserializer in BIST mode by setting the
BISTEN = H. The Des is now in the BIST mode and checks
the incoming serial payloads for errors. If an error in the pay-
load (1 to 24) is detected, the PASS pin will switch low for one
half of the clock period. During the BIST test, the PASS output
can be monitored and counted to determine the payload error
rate.
Step 3: To Stop the BIST mode, the deserializer BISTEN pin
is set Low. The deserializer stops checking the data and the
final test result is held on the PASS pin. If the test ran error
free, the PASS output will be High. If there was one or more
errors detected, the PASS output will be Low. The PASS out-
put state is held until a new BIST is run, the device is RESET,
or Powered Down. The BIST duration is user controlled by the
duration of the BISTEN signal.
Step 4: To return the link to normal operation, the ser and des
BISTEN input are set Low. The Link returns to normal oper-
ation.
Figure 26 shows the waveform diagram of a typical BIST test
for two cases. Case 1 is error free, and Case 2 shows one
with multiple errors. In most cases it is difficult to generate
errors due to the robustness of the link (differential data trans-
mission etc.), thus they may be introduced by greatly extend-
ing the cable length, faulting the interconnect, reducing signal
condition enhancements (De-Emphasis, VODSEL, or dese-
rializer Equalization).
30120943
FIGURE 25. BIST Mode Flow Diagram
BER Calculations
It is possible to calculate the approximate Bit Error Rate
(BER). The following is required:
• Pixel Clock Frequency (MHz)
• BIST Duration (seconds)
• BIST test Result (PASS)
The BER is less than or equal to one over the product of 24
times the RxCLKIN rate times the test duration. If we assume
a 65MHz RxCLKIN, a 10 minute (600 second) test, and a
PASS, the BERT is ≤ 1.07 X 10E-12
The BIST mode runs a check on the data payload bits. The
LOCK pin also provides a link status. It the recovery of the C0
and C1 bits does not reconstruct the expected clock signal,
the LOCK pin will switch Low. The combination of the LOCK
and At-Speed BIST PASS pin provides a powerful tool for
system evaluation and performance monitoring.
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