DS92LV0421 Datasheet, PDF (3/40 Pages) National Semiconductor (TI) – 10 - 75 MHz Channel Link II Serializer/Deserializer with LVDS Parallel Interface

DS92LV0421 Pin Diagram
DS92LV0421 — Top View
30120919
DS92LV0421 Pin Descriptions
Pin Name
Pin #
I/O, Type Description
Channel Link Parallel Input Interface
RxIN[3:0]+ 2, 33, 31, 29 I, LVDS True LVDS Data Input
This pair should have a 100 Ω termination for standard LVDS levels.
RxIN[3:0]- 1, 34, 32, 30,
28
I, LVDS
Inverting LVDS Data Input
This pair should have a 100 Ω termination for standard LVDS levels.
RxCLKIN+
35
I, LVDS True LVDS Clock Input
This pair should have a 100 Ω termination for standard LVDS levels.
RxCLKIN-
34
I, LVDS Inverting LVDS Clock Input
This pair should have a 100 Ω termination for standard LVDS levels.
Control and Configuration
PDB
23
I, LVCMOS Power-down Mode Input
w/ pull-down PDB = 1, Device is enabled (normal operation).
Refer to ”Power Up Requirements and PDB Pin” in the Applications Information Section.
PDB = 0, Device is powered down
When the Device is in the power-down state, the driver outputs (DOUT+/-) are both logic
high, the PLL is shutdown, IDD is minimized. Control Registers are RESET.
3
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