DS90UR241 Datasheet, PDF (4/24 Pages) National Semiconductor (TI) – 5-43 MHz DC-Balanced 24-Bit LVDS Serializer and Deserializer

Serializer Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
t_LLHT
LVDS Low-to-High Transition Time
R_L = 100Ω,
245
t_LHLT
LVDS High-to-Low Transition Time
C_L = 10 pF to GND,
(Figure 3)
264
t_DIS
t_DIH
t_HZD
t_LZD
t_ZHD
t_ZLD
t_PLD
t_SD
D_IN (0:23) Setup to TCLK
R_L = 100Ω,
4
D_IN (0:23) Hold from TCLK
C_L = 10 pF to GND,
(Note 7), (Figure 6)
4
D_OUT ± HIGH to TRI-STATE Delay R_L = 100Ω,
10
D_OUT ± LOW to TRI-STATE Delay
C_L = 10 pF to GND,
10
D_OUT ± TRI-STATE to HIGH Delay ^{(Note 4), (Figure 7)}
75
D_OUT ± TRI-STATE to LOW Delay
75
Serializer PLL Lock Time
R_L = 100Ω
Serializer Delay
R_L = 100Ω, PRE = OFF,
RAOFF = L, TRFB = H,
3.5T+2
(Figure 9)
R_L = 100Ω, PRE = OFF,
RAOFF = L, TRFB = L,
(Figure 9)
3.5T+2
TxOUT_E_O TxOUT_Eye_Opening.
5 MHz–43 MHz,
TxOUT_E_O centered on (tBIT/)2
(Notes 8, 9, 12),
0.80
(Figure 15)
Deserializer Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
Pin/Freq.
Min
Typ
t_RCP
Receiver out Clock Period
t_RCP = t_TCP,
PTOSEL = H
(Figure 11)
RCLK
23.25
t_RDC
RCLK Duty Cycle
PTOSEL = H
(Figure 11)
RCLK
45
50
t_CLH
LVCMOS/LVTTL
C_L = 4 pF
R_OUT [0:23],
Low-to-High Transition
(lumped load), RCLK, LOCK
Time
SLEW = H
t_CHL
LVCMOS/LVTTL
High-to-Low Transition
Time
t_CLH
LVCMOS/LVTTL
C_L = 4 pF
R_OUT [0:23],
Low-to-High Transition
(lumped load), RCLK, LOCK
Time
SLEW = L
t_CHL
LVCMOS/LVTTL
High-to-Low Transition
Time
Max
Units
550
ps
550
ps
ns
ns
15
ns
15
ns
150
ns
150
ns
10
ms
3.5T+10
ns
3.5T+10
ns
UI
Max Units
200
ns
55
%
2.5
ns
2.5
ns
3.5
ns
3.5
ns
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