DS90UR241 Datasheet, PDF (18/24 Pages) National Semiconductor (TI) – 5-43 MHz DC-Balanced 24-Bit LVDS Serializer and Deserializer

Functional Description
The DS90UR241 Serializer and DS90UR124 Deserializer
chipset is an easy-to-use transmitter and receiver pair that
sends 24-bits of parallel LVCMOS data over a single serial
LVDS link from 120 Mbps to 1.032 Gbps throughput. The
DS90UR241 transforms a 24-bit wide parallel LVCMOS data
into a single high speed LVDS serial data stream with em-
bedded clock. The DS90UR124 receives the LVDS serial
data stream and converts it back into a 24-bit wide parallel
data and recovered clock. The 24-bit Serializer/Deserializer
chipset is designed to transmit data up to 10 meters over
shielded twisted pair (STP) at clock speeds from 5 MHz to
43MHz.
The Deserializer can attain lock to a data stream without the
use of a separate reference clock source. The Deserializer
synchronizes to the Serializer regardless of data pattern,
delivering true automatic “plug and lock” performance. The
Deserializer recovers the clock and data by extracting the
embedded clock information and validating data integrity
from the incoming data stream and then deserializes the
data. The Deserializer monitors the incoming clock informa-
tion, determines lock status, and asserts the LOCK output
high when lock occurs. Each has a power down control to
enable efficient operation in various applications.
INITIALIZATION AND LOCKING MECHANISM
Initialization of the DS90UR241 and DS90UR124 must be
established before each device sends or receives data. Ini-
tialization refers to synchronizing the Serializer’s and Dese-
rializer’s PLL’s together. After the Serializers locks to the
input clock source, the Deserializer synchronizes to the Se-
rializers as the second and final initialization step.
Step 1: When V_DD is applied to both Serializer and/or Dese-
rializer, the respective outputs are held in TRI-STATE and
internal circuitry is disabled by on-chip power-on circuitry.
When V_DD reaches V_DD OK (2.2V) the PLL in Serializer
begins locking to a clock input. For the Serializer, the local
clock is the transmit clock, TCLK. The Serializer outputs are
held in TRI-STATE while the PLL locks to the TCLK. After
locking to TCLK, the Serializer block is now ready to send
data patterns. The Deserializer output will remain in TRI-
STATE while its PLL locks to the embedded clock informa-
tion in serial data stream. Also, the Deserializer LOCK output
will remain low until its PLL locks to incoming data and
sync-pattern on the RIN± pins.
Step 2: The Deserializer PLL acquires lock to a data stream
without requiring the Serializer to send special patterns. The
Serializer that is generating the stream to the Deserializer
will automatically send random (non-repetitive) data patterns
during this step of the Initialization State. The Deserializer
will lock onto embedded clock within the specified amount of
time. An embedded clock and data recovery (CDR) circuit
locks to the incoming bit stream to recover the high-speed
receive bit clock and re-time incoming data. The CDR circuit
expects a coded input bit stream. In order for the Deserial-
izer to lock to a random data stream from the Serializer, it
performs a series of operations to identify the rising clock
edge and validates data integrity, then locks to it. Because
this locking procedure is independent on the data pattern,
total random locking duration may vary. At the point when the
Deserializer’s CDR locks to the embedded clock, the LOCK
pin goes high and valid RCLK/data appears on the outputs.
Note that the LOCK signal is synchronous to valid data
appearing on the outputs. The Deserializer’s LOCK pin is a
convenient way to ensure data integrity is achieved on re-
ceiver side.
DATA TRANSFER
After lock is established, the Serializer inputs DIN0–DIN23
may be used to input data to the Serializer. Data is clocked
into the Serializer by the TCLK input. The edge of TCLK
used to strobe the data is selectable via the TRFB pin. TRFB
high selects the rising edge for clocking data and low selects
the falling edge. The Serializer outputs (DOUT±) are in-
tended to drive point-to-point connections or limited multi-
point applications.
CLK1, CLK0, DCA, DCB are four overhead bits transmitted
along the single LVDS serial data stream. The CLK1 bit is
always high and the CLK0 bit is always low. The CLK1 and
CLK0 bits function as the embedded clock bits in the serial
stream. DCB functions as the DC Balance control bit. It does
not require any pre-coding of data on transmit side. The DC
Balance bit is used to minimize the short and long-term DC
bias on the signal lines. This bit operates by selectively
sending the data either unmodified or inverted. The DCA bit
is used to validate data integrity in the embedded data
stream. Both DCA and DCB coding schemes are integrated
and automatically performed within Serializer and Deserial-
izer.
Serialized data and clock/control bits (24+4 bits) are trans-
mitted from the serial data output (DOUT±) at 28 times the
TCLK frequency. For example, if TCLK is 43 MHz, the serial
rate is 43 x 28 = 1.20 Giga bits per second. Since only 24 bits
are from input data, the serial “payload” rate is 24 times the
TCLK frequency. For instance, if TCLK = 43 MHz, the pay-
load data rate is 43 x 24 = 1.03 Gbps. TCLK is provided by
the data source and must be in the range of 5 MHz to 43
MHz nominal. The Serializer outputs (DOUT±) can drive a
point-to-point connection. The outputs transmit data when
the enable pin (DEN) is high, TPWDNB is high. The DEN pin
may be used to TRI-STATE the outputs when driven low.
When the Deserializer channel attains lock to the input from
a Serializer, it drives its LOCK pin high and synchronously
delivers valid data and recovered clock on the output. The
Deserializer locks onto the embedded clock, uses it to gen-
erate multiple internal data strobes, and then drives the
recovered clock to the RCLK pin. The recovered clock
(RCLK output pin) is synchronous to the data on the
ROUT[23:0] pins. While LOCK is high, data on ROUT[23:0]
is valid. Otherwise, ROUT[23:0] is invalid. The polarity of the
RCLK edge is controlled by the RRFB input. ROUT(0-23),
LOCK and RCLK outputs will each drive a maximum of 4 pF
load with a 43 MHz clock. REN controls TRI-STATE for
ROUTn and the RCLK pin on the Deserializer.
RESYNCHRONIZATION
If the Deserializer loses lock, it will automatically try to re-
establish lock. For example, if the embedded clock edge is
not detected one time in succession, the PLL loses lock and
the LOCK pin is driven low. The Deserializer then enters the
operating mode where it tries to lock to a random data
stream. It looks for the embedded clock edge, identifies it
and then proceeds through the locking process.
The logic state of the LOCK signal indicates whether the
data on ROUT is valid; when it is high, the data is valid. The
system must monitor the LOCK pin to determine whether
data on the ROUT is valid.
POWERDOWN
The Powerdown state is a low power sleep mode that the
Serializer and Deserializer may use to reduce power when
no data is being transferred. The TPWDNB and RPWDNB
are used to set each device into power down mode, which
www.national.com
18