DS90UR241 Datasheet, PDF (19/24 Pages) National Semiconductor (TI) – 5-43 MHz DC-Balanced 24-Bit LVDS Serializer and Deserializer

Functional Description (Continued)
reduces supply current to the µA range. The Serializer enters
powerdown when the TPWDNB pin is driven low. In power-
down, the PLL stops and the outputs go into TRI-STATE,
disabling load current and reducing supply. To exit Power-
down, TPWDNB must be driven high. When the Serializer
exits Powerdown, its PLL must lock to TCLK before it is
ready for the Initialization state. The system must then allow
time for Initialization before data transfer can begin. The
Deserializer enters powerdown mode when RPWDNB is
driven low. In powerdown mode, the PLL stops and the
outputs enter TRI-STATE. To bring the Deserializer block out
of the powerdown state, the system drives RPWDNB high.
Both the Serializer and Deserializer must reinitialize and
relock before data can be transferred. The Deserializer will
initialize and assert LOCK high until it is locked to the input
clock.
TRI-STATE
For the Serializer, TRI-STATE is entered when the DEN or
TPWDNB pin is driven low. This will TRI-STATE both driver
output pins (DOUT+ and DOUT−). When DEN is driven high,
the serializer will return to the previous state as long as all
other control pins remain static (TPWDNB, TRFB).
When you drive the REN or RPWDNB pin low, the Deseri-
alizer enters TRI-STATE. Consequently, the receiver output
pins (ROUT0–ROUT23) and RCLK will enter TRI-STATE.
The LOCK output remains active, reflecting the state of the
PLL. The Deserializer input pins are high impedance during
receiver powerdown (RPWDNB low) and power-off (V_DD =
0V).
PRE-EMPHASIS
The DS90UR241 features a Pre-Emphasis function used to
compensate for long or lossy transmission media. Cable
drive is enhanced with a user selectable Pre-Emphasis fea-
ture that provides additional output current during transitions
to counteract cable loading effects. The transmission dis-
tance will be limited by the loss characteristics and quality of
the media. Pre-Emphasis adds extra current during LVDS
logic transition to reduce the cable loading effects and in-
crease driving distance. In addition, Pre-Emphasis helps
provide faster transitions, increased eye openings, and im-
proved signal integrity. To enable the Pre-Emphasis function,
the “PRE” pin requires one external resistor (Rpre) to Vss in
order to set the additional current level. Pre-Emphasis
strength is set via an external resistor (Rpre) applied from
min to max (floating to 6kΩ) at the “PRE” pin. A lower input
resistor value on the ”PRE” pin increases the magnitude of
dynamic current during data transition. There is an internal
current source based on the following formula: PRE = (Rpre
≥ 6kΩ); I_MAX = [(1.2/Rpre) x 20 x 2]. The ability of the
DS90UR241 to use the Pre-Emphasis feature will extend the
transmission distance up to 10 meters in most cases.
AC-COUPLING AND TERMINATION
The DS90UR241 and DS90UR124 supports AC-coupled in-
terconnects through integrated DC balanced encoding/
decoding scheme. To use AC coupled connection between
the Serializer and Deserializer, insert external AC coupling
capacitors in series in the LVDS signal path as illustrated in
Figure 18. The Deserializer input stage is designed for AC-
coupling by providing a built-in AC bias network which sets
the internal V_CM to +1.8V. With AC signal coupling, capaci-
tors provide the ac-coupling path to the signal input.
For the high-speed LVDS transmissions, the smallest avail-
able package should be used for the AC coupling capacitor.
This will help minimize degradation of signal quality due to
package parasitics. The most common used capacitor value
for the interface is 100 nF (0.1 uF) capacitor.
A termination resistor across DOUT± and RIN± is also
required for proper operation to be obtained. The termination
resistor should be equal to the differential impedance of the
media being driven. This should be in the range of 90 to 132
Ohms. 100 Ohms is a typical value common used with
standard 100 Ohm transmission media. This resistor is re-
quired for control of reflections and also to complete the
current loop. It should be placed as close to the Serializer
DOUT± outputs and Deserializer RIN± inputs to minimize
the stub length from the pins. To match with the deferential
impedance on the transmission line, the LVDS I/O are termi-
nated with 100 ohm resistors on Serializer DOUT± outputs
pins and Deserializer RIN± input pins.
PROGRESSIVE TURN–ON (PTO)
The DS90UR124 Deserializer offers two types of Progres-
sive Turn-On modes (Fixed-PTO and PTO Frequency
Spread) to help reduce EMI, simultaneous switching noise,
and system ground bounce. For Fixed-PTO mode, the De-
serializer ROUT[23:0] outputs are grouped into three groups
of eight, with each group switching about 2 or 1 UI apart in
phase from RCLK for Group 1 and Groups 2, 3 respectively.
In the PTO Frequency Spread mode, ROUT[23:0] are also
grouped into three groups of eight, with each group is sepa-
rated out of phase with the adjacent groups (see Figure 12).
Note that in the PTO Frequency Spread operating mode
RCLK is also spreading and separated by 1 UI.
@SPEED-BIST TEST FEATURE
To assist vendors with test verification, the DS90UR241/
DS90UR124 is equipped with built-in self-test (BIST) capa-
bility to support both system manufacturing and field diag-
nostics. BIST mode is intended to check the entire high-
speed serial link at full link-speed, without the use of
specialized and expensive test equipment. This feature pro-
vides a simple method for a system host to perform diagnos-
tic testing of both Serializer and Deserializer. The BIST
function is easily configured through the 2 control pins on the
DS90UR124. When the BIST mode is activated, the Serial-
izer has the ability to transfer an internally generated PRBS
data pattern. This pattern traverses across interconnecting
links to the Deserializer. The DS90UR124 includes an on-
chip PRBS pattern verification circuit that checks the data
pattern for bit errors and reports any errors on the data
output pins on the Deserializer.
The @SPEED-BIST feature uses 2 signal pins (BISTEN and
BISTM) on the DS90UR124 Deserializer. The BISTEN and
BISTM pins together determine the functions of the BIST
mode. The BISTEN signal (HIGH) activates the test feature
on the Deserializer. After the BIST mode is enabled, all the
data input channels DIN[23:0] on the DS90UR241 Serializer
must be set logic LOW or floating in order for Deserializer to
start accepting data. An input clock signal (TCLK) for the
Serializer must also be applied during the entire BIST opera-
tion. The BISTM pin selects error reporting status mode of
the BIST function. When BIST is configured in the error
status mode (BISTM = LOW), each of the ROUT[23:0] out-
puts will correspond to bit errors on a cycle-by-cycle basis.
The result of bit mismatches are indicated on the respective
parallel inputs on the ROUT[23:0] data output pins. In the
BIST error-count accumulator mode (BISTM = HIGH), an
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