DS90UR241 Datasheet, PDF (1/24 Pages) National Semiconductor (TI) – 5-43 MHz DC-Balanced 24-Bit LVDS Serializer and Deserializer

PRELIMINARY
September 2006
DS90UR241/DS90UR124
5-43 MHz DC-Balanced 24-Bit LVDS Serializer and
Deserializer
General Description
The DS90UR241/124 Chipset translates a 24-bit parallel bus
into a fully transparent data/control LVDS serial stream with
embedded clock information. This single serial stream sim-
plifies transferring a 24-bit bus over PCB traces and cable by
eliminating the skew problems between parallel data and
clock paths. It saves system cost by narrowing data paths
that in turn reduce PCB layers, cable width, and connector
size and pins.
The DS90UR241/124 incorporates LVDS signaling on the
high-speed I/O. LVDS provides a low power and low noise
environment for reliably transferring data over a serial trans-
mission path. By optimizing the Serializer output edge rate
for the operating frequency range EMI is further reduced.
In addition the device features pre-emphasis to boost signals
over longer distances using lossy cables. Internal DC bal-
anced encoding/decoding is used to support AC-Coupled
interconnects. Using National Semiconductor’s proprietary
random lock, the Serializer’s parallel data are randomized to
the Deserializer without the need of REFCLK.
Features
n 5 MHz–43 MHz embedded clock and DC-Balanced 24:1
and 1:24 data transmission
n User defined pre-emphasis driving ability through
external resistor on LVDS outputs and capable to drive
up to 10 meters shielded twisted-pair cable
n User selectable clock edge for parallel data on both
Transmitter and Receiver
n Supports AC-coupling data transmission
n Individual power-down controls for both Transmitter and
Receiver
n 1.8V V_CM at LVDS input side
n Embedded clock CDR (clock and data recovery) on
Receiver and no source of reference clock needed
n All codes RDL (random data lock) to support
hot-pluggable applications
n LOCK output flag to ensure data integrity at Receiver
side
n Balanced T_SETUP/T_HOLD between RCLK and RDATA on
Receiver side
n Adjustable PTO (progressive turn-on) LVCMOS outputs
on Receiver to minimize EMI and SSO effects
n @Speed BIST to validate link integrity
n All LVCMOS inputs and control pins have internal
pulldown
n On-chip filters for PLLs on Transmitter and Receiver
n 48-pin TQFP package for Transmitter and 64-pin TQFP
package for Receiver
n Pure CMOS .35 µm process
n Power supply range 3.3V ± 10%
n Temperature range –40˚C to +105˚C
n Greater than 8 kV HBM ESD structure
n Meets ISO 10605 ESD compliance
n Backwards compatible with DS90C241/DS90C124
Block Diagram
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