DS90UR241 Datasheet, PDF (10/24 Pages) National Semiconductor (TI) – 5-43 MHz DC-Balanced 24-Bit LVDS Serializer and Deserializer

AC Timing Diagrams and Test Circuits (Continued)
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FIGURE 11. Deserializer Setup and Hold Times and PTO, PTOSEL = H
Group 1 will be latched internally by sequence of (early 2UI, late 1UI, early 1UI, late 2UI)
Group 2 will be latched internally by sequence of (late 1UI, early 1UI, late 2UI, early 2UI)
Group 3 will be latched internally by sequence of (early 1UI, late 2UI, early 2UI, late 1UI)
FIGURE 12. Deserializer Setup and Hold Times and PTO Spread, PTOSEL = L
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