DS90UR241 Datasheet, PDF (14/24 Pages) National Semiconductor (TI) – 5-43 MHz DC-Balanced 24-Bit LVDS Serializer and Deserializer

Pin Descriptions (Continued)
Pin # Pin Name
I/O/PWR
Description
DS90UR124 DESERIALIZER PIN DESCRIPTIONS
46
VDDR0
VDD
Digital Voltage supply, LOGIC POWER
47
VSSR0
GND
Digital Ground, LOGIC GROUND
40
VDDOR1
VDD
Digital Voltage supply, LVCMOS/LVTTL Output POWER
39
VSSOR1
GND
Digital Ground, LVCMOS/LVTTL Output GROUND
26
VDDOR2
VDD
Digital Voltage supply, LVCMOS/LVTTL Output POWER
25
VSSOR2
GND
Digital Ground, LVCMOS/LVTTL Output GROUND
11
VDDOR3
VDD
Digital Voltage supply, LVCMOS/LVTTL Output POWER
12
VSSOR3
GND
Digital Ground, LVCMOS/LVTTL Output GROUND
53
R_IN+
LVDS_I
54
R_IN−
LVDS_I
50
RESRVD
CMOS_I
Receiver LVDS true (+) INput
Receiver LVDS inverted (−) INput
RESeRVeD - MUST tie Low
55
RRFB
CMOS_I
Receiver Rising Falling Bar clock Edge Select
60
REN
CMOS_I
RRFB = H; R_OUT LVCMOS/LVTTL Output clocked on Rising CLK
RRFB = L; R_OUT LVCMOS/LVTTL Output clocked on Falling CLK
Receiver ENable, (ACTIVE H)
REN = L; Disabled, R_OUT[23-0] and RCLK TRI-STATED, PLL still operational
REN = H; ENabled
48
RPWDNB
CMOS_I
Receiver PoWer DowN Bar (ACTIVE L)
RPWDNB = L; Disabled, R_OUT[23-0], RCLK, and LOCK are TRI-STATED in stand-by
mode, PLL is shutdown
RPWDNB = H; ENabled
49
PTOSEL
CMOS_I
Progressive Turn On SELect
PTO = L (default);
PTO = H; PTO Spread (Figure 12)
61
BISTEN
COMS_I
@speed_BIST ENable (ACTIVE H)
BISTEN = L; (default), OFF
BISTEN = H; BIST enabled. Set DS90UR241 D_IN[23-0] all LOW or floating. Check
PASS condition.
62
BISTM
CMOS_I
BIST error reporting Mode selection
BISTM = L; (default), Status of all R_OUT with respective bit error on cycle-by-cycle basis
BISTM = H; Total accumulated bit error counter on R[7:0] (up to 255)
63
RAOFF
CMOS_I
Additional Randomizer OFF (ACTIVE H)
RAOFF = L; (default) Additional randomization ON
RAOFF = H; additional randomization OFF (backwards compatible with DS90C124)
64
SLEW
CMOS_I
LVCMOS/LVTTL Output SLEW rate control.
SLEW = 0; (default)
SLEW = 1; 2X drive/edge rate
23
LOCK
CMOS_O
LOCK indicates the status of the receiver PLL
LOCK = L; receiver PLL is unlocked, R_OUT[23-0] and RCLK are TRI-STATED
LOCK = H; receiver PLL is locked
35-38, R_OUT[7:0]
41-44
CMOS_O
Receiver Outputs – Group 1
19-22, R_OUT[15:8]
27-30
CMOS_O
Receiver Outputs – Group 2
7-10, R_OUT[23:16] CMOS_O
13-16
Receiver Outputs – Group 3
24
RCLK
CMOS_O
Recovered CLocK. Parallel data rate clock recovered from the embedded clock.
45
PASS
CMOS_O
PASS = L; BIST failure
PASS = H; LOCK = H before BIST can be enabled, then 1x10^-9 error rate achieved
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