DS90UR241 Datasheet, PDF (3/24 Pages) National Semiconductor (TI) – 5-43 MHz DC-Balanced 24-Bit LVDS Serializer and Deserializer

Electrical Characteristics (Continued)
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
Pin/Freq.
Min Typ Max Units
LVDS DC SPECIFICATIONS
V_TH
Differential Threshold High V_CM = +1.8V
Voltage
Rx: R_IN+, R_IN−
+100 mV
V_TL
Differential Threshold Low
Voltage
−100
mV
I_IN
Input Current
V_OD
∆V_OD
Output Differential Voltage
(D_OUT+)– (D_OUT−)
Output Differential Voltage
Unbalance
V_IN = +2.4V,
V_DD = 3.6V or 0V
V_IN = 0V, V_DD = 3.6V or 0V
R_L = 100Ω, w/o pre-emphasis
R_L = 100Ω, w/o pre-emphasis
Tx: D_OUT+, D_OUT−
±100 ±250 µA
±100 ±250 µA
300 500 700 mV
1 50 mV
V_OS
∆V_OS
I_OS
Offset Voltage
Offset Voltage Unbalance
Output Short Circuit Current
R_L = 100Ω, w/o pre-emphasis
R_L = 100Ω, w/o pre-emphasis
D_OUT = 0V, D_IN = H,
TPWDNB = 2.4V
1.00 1.25 1.50 V
3 50 mV
−2.0
−8.0 mA
I_OZ
TRI-STATE Output Current TPWDNB = 0V,
D_OUT = 0V OR V_DD
TPWDNB = 2.4V, DEN = 0V
D_OUT = 0V OR V_DD
TPWDNB = 2.4V, DEN = 2.4V,
D_OUT = 0V OR V_DD
NO LOCK (NO TCLK)
−15 ±1 15 µA
−15 ±1 15 µA
−15 ±1 15 µA
SER/DES SUPPLY CURRENT (DVDD*, PVDD* AND AVDD* PINS) *DIGITAL, PLL, AND ANALOG VDDS
I_DDT
Serializer
Total Supply Current
(includes load current)
R_L = 100Ω, PRE = OFF,
RAOFF = H
R_L = 100Ω, PRE = 12 kΩ,
RAOFF = H
f = 43 MHz,
CHECKER BOARD
Pattern (Figure 1)
60 85 mA
65 90 mA
I_DDTZ
Serializer
TPWDNB = 0V
Supply Current Power-down
200 800 µA
I_DDR
Deserializer
Total Supply Current
(includes load current)
C_L = 4 pF,
SLEW = H/L
f = 43 MHz,
CHECKER BOARD
Pattern
LVCMOS/LVTTL Output
(Figure 2)
95 mA
C_L = 4 pF,
SLEW = H/L
f = 43 MHz,
RANDOM pattern
LVTTL Output
90 mA
I_DDRZ Deserializer
RPWDNB = 0V
Supply Current Power-down
200 800 µA
Serializer Timing Requirements for TCLK
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
t_TCP
t_TCIH
t_TCIL
t_CLKT
t_JIT
Transmit Clock Period
Transmit Clock High Time
Transmit Clock Low Time
TCLK Input Transition Time
TCLK Input Jitter
(Figure 6)
(Figure 5)
(Note 8)
23.25
0.3T
0.3T
T
0.5T
0.5T
2.5
Max
200
0.7T
0.7T
±100
Units
ns
ns
ns
ns
ps
3
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