COP87L84BC Datasheet, PDF (35/54 Pages) National Semiconductor (TI) – 8-Bit CMOS OTP Microcontrollers with 16k Memory, Comparators, and CAN Interface

Frame Formats (Continued)
FIGURE 32. Resynchronization 1
DS101137-67
FIGURE 33. Resynchronization 2
DS101137-68
Comparators
The device has two differential comparators. Port L is used
for the comparators. The output of the comparators is multi-
plexed out to two pins. The following are the Port L assign-
ments:
L6 Comparator 2 output
L5 Comparator 2 negative input
L4 Comparator 2 positive input
L3 Comparator 2 negative input
L2 Comparator 1 output
L1 Comparator 1 negative input
L0 Comparator 1 positive input
Additionally the comparator output can be connected inter-
nally to the L-Port pin of the respective positive input and
thereby generate an interrupt using the L-Port interrupt
structure (neg/pos. edge, enable/disable).
Note that in Figure 34, pin L6 has a second alternate function
of supporting the PWM0 output. The comparator 2 output
MUST be disabled in order to use PWM0 output on L6.
Figure 34 shows the Comparator Block Diagram.
COMPARATOR CONTROL REGISTER (CMPSL) (00D3)
These bits reside in the Comparator Register
CMP2 CMP2 CMP2 CMP2 CMP1 CMP1 CMP1 Re-
SEL OE RD EN OE RD EN served
Bit 7
Bit 0
The register contains the following bits:
CMP2SEL Selects which L port pin to use for comparator2
negative input. (CMP2SEL = 0 selects L5;
CMP2SEL = 1 selects pin L3).
CMP2OE Enables comparator 2 output (“1”=enable),
CMP2EN bit must be set to enable this function.
CMP2RD Reads comparator 2 output internally
(CMP2EN=1) Read-only, reads as a “0” if com-
parator not enabled.
CMP2EN Enables comparator 2 (“1”=enable). If compara-
tor 2 is disabled the associated L-pins can be
used as standard I/O.
CMP1OE Enables comparator 1 output (“1”=enable),
CMP1EN bit must be set to enable this function.
CMP1RD Reads comparator 1 output internally
(CMP1EN=1) Read-only, reads as a “0” if com-
parator not enabled.
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