COP87L84BC Datasheet, PDF (24/54 Pages) National Semiconductor (TI) – 8-Bit CMOS OTP Microcontrollers with 16k Memory, Comparators, and CAN Interface

Functional Block Description of
the CAN Interface (Continued)
TRANSMIT CONTROL/STATUS (TCNTL) (00BB)
NS1 NS0 TERR RERR CEIE TIE RIE TXSS
Bit 7
Bit 0
NS1..NS0 Node Status, i.e., Error Status.
TABLE 6. Node Status
NS1
NS0
Output
0
0
Error active
0
1
Error passive
1
0
Bus off
1
1
Bus off
The Node Status bits are read only.
TERR Transmit Error
This bit is automatically set when an error occurs during the
transmission of a frame. TERR can be programmed to gen-
erate an interrupt by setting the Can Error Interrupt Enable
bit (CEIE). This bit must be cleared by the user’s software.
Note: This is used for messages for more than two bytes. If an error occurs
during the transmission of a frame with more than 2 data bytes, the us-
er’s software has to handle the correct reloading of the data bytes to
the TxD registers for retransmission of the frame. For frames with 2 or
fewer data bytes the interface logic of this chip does an automatic re-
transmission. Regardless of the number of data bytes, the user’s soft-
ware must reset this bit if CEIE is enabled. Otherwise a new interrupt
will be generated immediately after return from the interrupt service
routine.
RERR Receiver Error
This bit is automatically set when an error occurred during
the reception of a frame. RERR can be programmed to gen-
erate an interrupt by setting the Can Error Interrupt Enable
bit (CEIE). This bit has to be cleared by the user’s software.
CEIE CAN Error Interrupt Enable
If set by the user’s software, this bit enables the transmit and
receive error interrupts. The interrupt pending flags are
TERR and RERR. Resetting this bit with a pending error in-
terrupt will inhibit the interrupt, but will not clear the cause of
the interrupt (RERR or TERR). If the bit is then set without
clearing the cause of the interrupt, the interrupt will reoccur.
TIE Transmit Interrupt Enable
If set by the user’s software, this bit enables the transmit in-
terrupt. (See TBE and TXPND.) Resetting this bit with a
pending transmit interrupt will inhibit the interrupt, but will not
clear the cause of the interrupt. If the bit is then set without
clearing the cause of the interrupt, the interrupt will reoccur.
RIE Receive Interrupt Enable
If set by the user’s software, this bit enables the receive in-
terrupt or a remote transmission request interrupt (see RBF,
RFV and RRTR). Resetting this bit with a pending receive in-
terrupt will inhibit the interrupt, but will not clear the cause of
the interrupt. If the bit is then set without clearing the cause
of the interrupt, the interrupt will reoccur.
TXSS Transmission Start/Stop
This bit is set by the user’s software to initiate the transmis-
sion of a frame. Once this bit is set, a transmission is pend-
ing, as indicated by the TXPND flag being set. It can be reset
by software to cancel a pending transmission. Resetting the
TXSS bit will only cancel a transmission, if the transmission
of a frame hasn’t been started yet (bus idle), if arbitration has
been lost (receiving) or if an error occurs during transmis-
sion. If the device has already started transmission (won ar-
bitration) the TXPND and TXSS flags will stay set until the
transmission is completed, even if the user’s software has
written zero to the TXSS bit. If one or more data bytes are to
be transmitted, care must be taken by the user, that the
Transmit Data Register(s) have been loaded before the
TXSS bit is set. TXSS will be cleared on three conditions
only: Successful completion of a transmitted message; suc-
cessful cancellation of a pending transmision; Transition of
the CAN interface to the bus-off state.
DS101137-52
FIGURE 20. Acceptance Filter Block-Diagram
Writing a zero to the TXSS bit will request cancellation of a
pending transmission but TXSS will not be cleared until
completion of the operation. If an error occurs during trans-
mission of a frame, the logic will check for cancellation re-
quests prior to restarting transmission. If zero has been writ-
ten to TXSS, retransmission will be canceled.
RECEIVE/TRANSMIT STATUS (RTSTAT) (Address
X’00BC)
TBE TXPND RRTR ROLD RORN RFV RCV RBF
1
0
0
0
0
0
0
0
Bit 7
Bit 0
This register is read only.
TBE Transmit Buffer Empty
This bit is set as soon as the TxD2 register is copied into the
Rx/Tx shift register, i.e., the 1st data byte of each pair has
been transmitted. The TBE bit is automatically reset if the
TxD2 register is written (the user should write a dummy byte
to the TxD2 register when transmitting an odd number of
bytes of zero bytes). TBE can be programmed to generate
an interrupt by setting the Transmit Interrupt Enable bit (TIE).
When servicing the interrupt the user has to make sure that
TBE gets cleared by executing a WRITE instruction on the
TxD2 register, otherwise a new interrupt will be generated
immediately after return from the interrupt service routine.
The TBE bit is read only. It is set to 1 upon reset. TBE is also
set upon completion of transmission of a valid message.
TXPND Transmission Pending
This bit is set as soon as the Transmit Start/Stop (TXSS) bit
is set by the user. It will stay set until the frame was success-
fully transmitted, until the transmission was successfully can-
celed by writing zero to the Transmission Start/Stop bit
(TXSS), or the device enters the bus-off state. Resetting the
TXSS bit will only cancel a transmission if the transmission
of a frame hasn’t been started yet (bus idle) or if arbitration
has been lost (receiving). If the device has already started
transmission (won arbitration) the TXPND flag will stay set
until the transmission is completed, even if the user’s soft-
ware has requested cancellation of the message. If an error
occurs during transmission, a requested cancellation may
occur prior to the begining of retransmission.
RRTR Received Remote Transmission Request
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