COP87L84BC Datasheet, PDF (12/54 Pages) National Semiconductor (TI) – 8-Bit CMOS OTP Microcontrollers with 16k Memory, Comparators, and CAN Interface

Timers (Continued)
while the pin T1B is an input to the timer block. The powerful
and flexible timer block allows the device to easily perform all
timer functions with minimal software overhead. The timer
block has three operating modes: Processor Independent
PWM mode, External Event Counter mode, and Input Cap-
ture mode.
The control bits T1C3, T1C2, and T1C1 allow selection of the
different modes of operation.
Mode 1. Processor Independent PWM Mode
As the name suggests, this mode allows the device to gen-
erate a PWM signal with very minimal user intervention.
The user only has to define the parameters of the PWM sig-
nal (ON time and OFF time). Once begun, the timer block will
continuously generate the PWM signal completely indepen-
dent of the microcontroller. The user software services the
timer block only when the PWM parameters require updat-
ing.
In this mode the timer T1 counts down at a fixed rate of t_c.
Upon every underflow the timer is alternately reloaded with
the contents of supporting registers, R1A and R1B. The very
first underflow of the timer causes the timer to reload from
the register R1A. Subsequent underflows cause the timer to
be reloaded from the registers alternately beginning with the
register R1B.
The T1 Timer control bits, T1C3, T1C2 and T1C1 set up the
timer for PWM mode operation.
Figure 9 shows a block diagram of the timer in PWM mode.
The underflows can be programmed to toggle the T1A output
pin. The underflows can also be programmed to generate in-
terrupts.
Underflows from the timer are alternately latched into two
pending flags, T1PNDA and T1PNDB. The user must reset
these pending flags under software control. Two control en-
able flags, T1ENA and T1ENB, allow the interrupts from the
timer underflow to be enabled or disabled. Setting the timer
enable flag T1ENA will cause an interrupt when a timer un-
derflow causes the R1A register to be reloaded into the
timer. Setting the timer enable flag T1ENB will cause an in-
terrupt when a timer underflow causes the R1B register to be
reloaded into the timer. Resetting the timer enable flags will
disable the associated interrupts.
Either or both of the timer underflow interrupts may be en-
abled. This gives the user the flexibility of interrupting once
per PWM period on either the rising or falling edge of the
PWM output. Alternatively, the user may choose to interrupt
on both edges of the PWM output.
FIGURE 8. Timers T1 and T0
DS101137-8
FIGURE 9. Timer 1 in PWM MODE
DS101137-9
Mode 2. External Event Counter Mode
This mode is quite similar to the processor independent
PWM mode described above. The main difference is that the
timer, T1, is clocked by the input signal from the T1A pin. The
T1 timer control bits, T1C3, T1C2 and T1C1 allow the timer
to be clocked either on a positive or negative edge from the
T1A pin. Underflows from the timer are latched into the
T1PNDA pending flag. Setting the T1ENA control flag will
cause an interrupt when the timer underflows.
In this mode the input pin T1B can be used as an indepen-
dent positive edge sensitive interrupt input if the T1ENB con-
trol flag is set. The occurrence of a positive edge on the T1B
input pin is latched into the T1PNDB flag.
Figure 10 shows a block diagram of the timer in External
Event Counter mode.
Note: The PWM output is not available in this mode since the T1A pin is be-
ing used as the counter input clock.
Mode 3. Input Capture Mode
The device can precisely measure external frequencies or
time external events by placing the timer block, T1, in the in-
put capture mode.
In this mode, the timer T1 is constantly running at the fixed t_c
rate. The two registers, R1A and R1B, act as capture regis-
ters. Each register acts in conjunction with a pin. The register
R1A acts in conjunction with the T1A pin and the register
R1B acts in conjunction with the T1B pin.
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