COP87L84BC Datasheet, PDF (34/54 Pages) National Semiconductor (TI) – 8-Bit CMOS OTP Microcontrollers with 16k Memory, Comparators, and CAN Interface

Frame Formats (Continued)
• An ACK-error occurs in an error passive device and no
“dominant” bits are detected while sending the passive
error flag. This does not lead to an incrementation of the
TEC.
• If only one device is on the bus and this device transmits
a message, it will get no acknowledgment. This will be
detected as an error and message will be repeated.
When the device goes “error passive” and detects an ac-
knowledge error, the TEC counter is not incremented.
Therefore the device will not go from “error passive” to
the “bus off” state due to such a condition.
FIGURE 30. CAN Bus States
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Figure 30 shows the connection of different bus states ac-
cording to the error counters.
SYNCHRONIZATION
Every receiver starts with a “hard synchronization” on the
falling edge of the SOF bit. One bit time consists of four bit
segments: Synchronization segment, propagation segment,
phase segment 1 and phase segment 2.
A falling edge of the data signal should be in the synchroni-
zation segment. This segment has the fixed length of one
time quanta. To compensate for the various delays within a
network, the propagation segment is used. Its length is pro-
grammable from 1 to 8 time quanta. Phase segment 1 and
phase segment 2 are used to resynchronize during an active
frame. The length of these segments is from 1 to 8 time
quanta long.
Two types of synchronization are supported:
Hard synchronization is done with the falling edge on the
bus while the bus is idle, which is then interpreted as the
SOF. It restarts the internal logic.
Soft synchronization is used to lengthen or shorten the bit
time while a data or remote frame is received. Whenever a
falling edge is detected in the propagation segment or in
phase segment 1, the segment is lengthened by a specific
value, the resynchronization jump width (see Figure 32).
If a falling edge lies in the phase segment 2 (as shown in Fig-
ure 32) it is shortened by the resynchronization jump width.
Only one resynchronization is allowed during one bit time.
The sample point lies between the two phase segments and
is the point where the received data is supposed to be valid.
The transmission point lies at the end of phase segment 2 to
start a new bit time with the synchronization segment.
Note 12: The resynchronization jump width (RJW) is automatically deter-
mined from the programmed value of PS. If a soft resynchronization is done
during phase segment 1 or the propagation segment, then RJW will either be
equal to 4 internal CAN clocks (CKI/(1 + divider)) or the programmed value of
PS, whichever is less. PS2 will never be shorter than 1 internal CAN clock.
Note 13: (PS1 — BTL settings any PSC setting) The PS1 of the BTL should
always be programmed to values greater than 1. To allow device resynchro-
nization for positive and negative phase errors on the bus. (if PS1 is pro-
grammed to one, a bit time could only be lengthened and never shortened
which basically disables half of the synchronization).
A) Synchronization segment
B) Propagation segment
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FIGURE 31. Bit Timing
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