COP87L84BC Datasheet, PDF (25/54 Pages) National Semiconductor (TI) – 8-Bit CMOS OTP Microcontrollers with 16k Memory, Comparators, and CAN Interface

Functional Block Description of
the CAN Interface (Continued)
This bit is set when the remote transmission request (RTR)
bit in a received frame was set. It is automatically reset
through a read of the RXD1 register.
To detect RRTR the user can either poll this flag or enable
the receive interrupt (the reception of a remote transmission
request will also cause an interrupt if the receive interrupt is
enabled). If the receive interrupt is enabled, the user should
check the RRTR flag in the service routine in order to distin-
guish between a RRTR interrupt and a RBF interrupt. It is the
responsibility of the user to clear this bit by reading the RXD1
register, before the next frame is received.
ROLD Received Overload Frame
This bit is automatically set when an Overload Frame was
received on the bus. It is automatically reset through a read
of the Receive/Transmit Status register. It is the responsibil-
ity of the user to clear this bit by reading the Receive/
Transmit Status register, before the next frame is received.
RORN Receiver Overrun
This bit is automatically set on an overrun of the receive data
register, i.e., if the user’s program does not maintain the
RxDn registers when receiving a frame. It it automatically re-
set through a read of the Receive/Transmit Status register. It
is the responsibility of the user to clear this bit by reading the
Receive/Transmit Status register before the next frame is re-
ceived.
RFV Received Frame Valid
This bit is set if the received frame is valid, i.e., after the pen-
ultimate bit of the End of Frame is received. It is automati-
cally reset through a read of the Receive/Transmit Status
register. It is the responsibility of the user to clear this bit by
reading the receive/transmit status register (RTSTAT), be-
fore the next frame is received. RFV will cause a Receive In-
terrupt if enabled by RIE. The user should be careful to read
the last data byte (RxD1) of odd length messages (1, 3, 5 or
7 data bytes) on receipt of RFV. RFV is the only indication
that the last byte of the message has been received.
RCV Receive Mode
This bit is set after the data length code of a message that
passes the device’s acceptance filter has been received. It is
automatically reset after the CRC-delimiter of the same
frame has been received. It indicates to the user’s software
that arbitration is lost and that data is coming in for that node.
RBF Receive Buffer Full
This bit is set if the second Rx data byte was received. It is
reset automatically, after the RxD1-Register has been read
by the software. RBF can be programmed to generate an in-
terrupt by setting the Receive Interrupt Enable bit (RIE).
When servicing the interrupt, the user has to make sure that
RBF gets cleared by executing a LD instruction from the
RxD1 register, otherwise a new interrupt will be generated
immediately after return from the interrupt service routine.
The RBF bit is read only.
TRANSMIT ERROR COUNTER (TEC) (Address X’00BD)
TEC7 TEC6 TEC5 TEC4
Bit 7
This register is read/write.
TEC3
TEC2
TEC1
TEC0
Bit 0
For test purposes and to identify the node status, the trans-
mit error counter, an 8-bit error counter, is mapped into the
data memory. If the lower seven bits of the counter overflow,
i.e., TEC7 is set, the device is error passive.
CAUTION
To prevent interference with the CAN fault confinement, the
user must not write to the REC/TEC registers. Both counters
are automatically updated following the CAN specification.
RECEIVE ERROR COUNTER (REC) (00BE)
ROVL REC6 REC5 REC4 REC3 REC2 REC1 REC0
Bit 7
Bit 0
This register is read/write.
ROVL receive error counter overflow
For test purposes and to identify the node status the receive
error counter, a 7-bit error counter, is mapped into the data
memory. If the counter overflows the ROVL bit is set to indi-
cate that the device is error passive and won’t transmit any
active error frames. If ROVL is set then the counter is frozen.
MESSAGE IDENTIFICATION
a. Transmitted Message
The user can select all 11 Transmit Identifier Bits to transmit
any message whigh fulfills the CAN2.0, part B spec without
an extended identifier (see note below). Fully automatic re-
transmission is supported for messages no longer than 2
bytes.
b. Received Messages
The lower four bits of the Receive Identifier are don’t care,
i.e., the controller will receive all messages that fit in that win-
dow (16 messages). The upper 7 bits can be defined by the
user in the Receive Identifier High Register to mask out
groups of messages. If the RIAF bit is set, all messages will
be received.
Note: The CAN interface tolerates the extended CAN frame format of 29
identifier bits and gives an acknowledgment. If an error occurs the re-
ceive error counter will be increased, and decreased if the frame is
valid.
BUS SYNCHRONIZATION DURING OPERATION
Resetting the TxEN1 and TxEN0 bits in Bus Control Register
will disable the output drivers and do a resynchronization to
the bus. All other CAN related registers and flags will be un-
affected.
Bus synchronization of the device is this case is done in the
following way:
If the output was disabled (TxEN1, TxEN0 = “0”) and either
TxEN1 or TxEN0, or both are set to 1, the device will not start
transmission or reception of a frame until eleven consecutive
“recessive” bits have been received.
A “bus off” condition will also cause the output drivers Tx1
and Tx0 to be at TRI-STATE (independent of the status of
TxEN1 and TxEN0). The device will switch from “bus off” to
“error active” mode as described under the FMOD-bit de-
scription (see Can Bus Control register). This will ensure that
the device is synchronized to the bus, before starting to
transmit or receive.
For information on bus synchronization and status of the
CAN related registers after external reset refer to the RESET
section.
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