COP87L84BC Datasheet, PDF (21/54 Pages) National Semiconductor (TI) – 8-Bit CMOS OTP Microcontrollers with 16k Memory, Comparators, and CAN Interface

Functional Block Description of
the CAN Interface (Continued)
Transceive Logic (TCL)
The TCL is a state machine which incorporates the bit stuff
logic and controls the output drivers, CRC logic and the
Rx/Tx shift registers. It also controls the synchronization to
the bus with the CAN clock signal generated by the BTL.
Error Management Logic (EML)
The EML is responsible for the fault confinement of the CAN
protocol. It is also responsible for changing the error
counters, setting the appropriate error flag bits and interrupts
and changing the error status (passive, active and bus off).
Cyclic Redundancy Check (CRC) Generator and
Register
The CRC Generator consists of a 15-bit shift register and the
logic required to generate the checksum of the destuffed bit-
stream. It informs the EML about the result of a receiver
checksum.
The checksum is generated by the polynomial:
χ¹⁵ + χ¹⁴ + χ¹⁰ + χ⁸ + χ⁷ + χ⁴ + χ³ + 1
Receive/Transmit (Rx/Tx) Registers
The Rx/Tx registers are 8-bit shift registers controlled by the
TCL and the BSP. They are loaded or read by the Interface
Management Logic, which holds the data to be transmitted
or the data that was received.
Bit Time Logic (BTL)
The bit time logic divider divides the CKI input clock by the
value defined in the CAN prescaler (CSCAL) and bus timing
register (CTIM). The resultig bit time (tcan) can be computed
by the formula:
Where divider is the value of the clock prescaler, PS is the
programmable value of phase segment 1 and 2 (1..8) and
PPS the programmed value of the propagation segment
(1..8) (located in CTIM).
Bus Timing Considerations
The internal architecture of the CAN interface has been op-
timized to allow fast software response times within mes-
sages of more than two data bytes. The TBE (Transmit
Buffer Empty) bit is set on the last bit of odd data bytes when
CAN internal sample points are high.
It is the user’s responsibility to ensure that the time between
setting TBE and a reload of TxD2 is longer than the length of
phase segment 2 as indicated in the following equation:
Table 2 shows examples of the minimum required t_LOAD for
different CSCAL settings based on a clock frequency of
10 MHz. Lower clock speeds require recalculation of the
CAN bit rate and the mimimum t_LOAD.
TABLE 2. CAN Timing (CKI = 10 MHz t_c = 1 µs)
PS CSCAL
4
3
CAN Bit Rate (kbit/s)
250
Minimum
t_LOAD (µs)
2.0
4
9
100
5.0
4
15
62
8.0
4
24
40
12.5
4
39
25
20
4
99
10
50
4
199
5
100
FIGURE 18. Bit Rate Generation
Figure 19 illustrates the minimum time required for t_LOAD.
DS101137-50
FIGURE 19. TBE Timing
21
DS101137-51
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