UPD784915B Datasheet, PDF (69/86 Pages) NEC – 16-BIT SINGLE-CHIP MICROCONTROLLERS

µPD784915B, 784916B
Other operations (TA = –10 to +70°C, VDD = AVDD = 4.5 to 5.5 V, VSS = AVSS = 0 V)
Parameter
Symbol
Condition
MIN.
Timer input signal low-level width
tWCTL When DFGIN, CFGIN, DPGIN, REEL0IN,
tCLK1
or REEL1IN logic level is input
Timer input signal high-level width
tWCTH When DFGIN, CFGIN, DPGIN, REEL0IN,
tCLK1
or REEL1IN logic level is input
Timer input signal valid edge input cycle tPERIN When DFGIN, CFGIN, or DPGIN is input
2
CSYNCIN low-level width
tWCR1L When digital noise elimination circuit is not used 8tCLK1
When digital noise elimination circuit is used 108tCLK1
(Bit 4 of INTM2 = 0)
When digital noise elimination circuit is used 180tCLK1
(Bit 4 of INTM2 = 1)
CSYNCIN high-level width
tWCR1H When digital noise elimination circuit is not used 8tCLK1
When digital noise elimination circuit is used 108tCLK1
(Bit 4 of INTM2 = 0)
When digital noise elimination circuit is used 180tCLK1
(Bit 4 of INTM2 = 1)
Digital noise
Eliminated pulse width tWSEP Bit 4 of INTM2 = 0
elimination
Bit 4 of INTM2 = 1
circuit
Passed pulse width
Bit 4 of INTM2 = 0
108tCLK1
Bit 4 of INTM2 = 1
180tCLK1
NMI low-level width
tWNIL VDD = AVDD = 2.7 to 5.5 V
10
NMI high-level width
tWNIH VDD = AVDD = 2.7 to 5.5 V
10
INTP0, INTP3 low-level widths
tWIPL0
2tCLK1
INTP0, INTP3 high-level widths
tWIPH0
2tCLK1
INTP1, KEY0 to KEY4 low-level widths tWIPL1 Mode other than STOP mode
2tCLK1
In STOP mode, for releasing STOP mode
10
INTP1, KEY0 to KEY4 high-level widths tWIPH1 Mode other than STOP mode
2tCLK1
In STOP mode, for releasing STOP mode
10
INTP2 low-level width
tWIPL2 In normal mode,
with main clock
Sampling = fCLK
Sampling = fCLK/128
2tCLK1
32^Note
Normal mode,
with subclock
Sampling = fCLK
Sampling = fCLK/128
61
7.9^Note
In STOP mode, for releasing STOP mode
10
INTP2 high-level width
tWIPH2 In normal mode,
with main clock
Sampling = fCLK
Sampling = fCLK/128
2tCLK1
32^Note
Normal mode,
with subclock
Sampling = fCLK
Sampling = fCLK/128
61
7.9^Note
In STOP mode, for releasing STOP mode
10
RESET low-level width
tWRSL
10
MAX. Unit
ns
ns
µs
ns
ns
ns
ns
ns
ns
104tCLK1 ns
176tCLK1 ns
ns
ns
µs
µs
ns
ns
ns
µs
ns
µs
ns
µs
µs
ms
µs
ns
µs
µs
ms
µs
µs
Note If a high or low level is successively input two times during the sampling period, a high or low level is
detected.
Remark tCKL1: operating clock cycle time of peripheral circuit (125 ns)
69