UPD784915B Datasheet, PDF (51/86 Pages) NEC – 16-BIT SINGLE-CHIP MICROCONTROLLERS

µPD784915B, 784916B
4.1.1 Vector interrupt
When an interrupt request is acknowledged, an interrupt processing program is executed according to the data
stored in the vector table area (the first address of the interrupt processing program created by the user).
Four levels of priorities can be specified by software for the vector interrupts of the µPD784916B.
4.1.2 Context switching
When an interrupt request is generated or when the BRKCS instruction is executed, a specific register bank is
selected by hardware, and execution branches to a vector address set in advance in the register bank. At the same
time, the current contents of the program counter (PC) and program status word (PSW) are saved to the registers
in the register bank. Because the contents of PC and PSW are not saved to the stack area, execution can be branched
to an interrupt processing routine more quickly than the vector interrupt.
Figure 4-2. Context Switching Operation When Interrupt Request Is Generated
<7> 0H
PC19-16 PC15-0
<6> Exchange
<2> Save
Bits 8-11 of temporary
register
<5> Save
Temporary register
<1> Save
PSW
Register bank n (n = 0-7)
A
X
B
C
R5
R4
R7
R6
V
VP
U
UP
T
D
E
W
H
L
Register bank
(0-7)
<3> Switching register bank
(RBS0 – RBS2 ← n)
<4> RSS ← 0
IE ← 0
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