UPD784915B Datasheet, PDF (34/86 Pages) NEC – 16-BIT SINGLE-CHIP MICROCONTROLLERS

µPD784915B, 784916B
(1) Timer 0 unit
Timer 0 unit creates head switching signal and pseudo VSYNC output timing from the PG and FG signals of the
drum motor.
This unit consists of an event counter (EC: 8 bits), four compare registers (ECC0 to ECC3), a timer (TM0: 16
bits), and three compare registers (CR00 to CR02).
A signal indicating coincidence between the value of timer 0 and the value of a compare register can be used
as the output trigger of the real-time output port.
(2) Free running counter unit
The free running counter unit detects the speed and phase of the drum motor, and the speed and reel speed
of the capstan motor.
This unit consists of a free running counter (FRC), six capture registers (CPT0 to CPT5), a VSYNC separation circuit,
and a HSYNC separation circuit.
(3) Timer 1 unit
Timer 1 unit is a reference timer unit synchronized with the frame cycle and creates the RECCTL signal, detects
the phase of the capstan motor, and detects the duty factor of the PBCTL signal. This unit consists of the following
three groups.
• Timer 1 (TM1), compare registers (CR10, CR11, and CR13), and capture register (CR12)
• Timer 3 (TM3), compare registers (CR30 and CR31), and capture register (CPT30)
• Event divider counter (EDV) and compare register (EDVC)
The TM1-CR13 coincidence signal can be used for automatic unmasking of VSYNC or as the output trigger of the
real-time output port.
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