UPD784915B Datasheet, PDF (68/86 Pages) NEC – 16-BIT SINGLE-CHIP MICROCONTROLLERS

µPD784915B, 784916B
AC Characteristics
CPU and peripheral circuit operation clock (TA = –10 to +70°C, VDD = AVDD = 4.5 to 5.5 V, VSS = AVSS = 0 V)
Parameter
CPU operation clock cycle time
Peripheral operation clock cycle time
Symbol
tCLK fXX = 16 MHz
fXX = 16 MHz
fXX = 8 MHz
tCLK1
fXX = 16 MHz
fXX = 8MHz
Condition
VDD = AVDD = 4.0 to 5.5 V
CPU Function only
low-frequency oscillation mode
(Bit 7 of CC = 1)
low-frequency oscillation mode
(Bit 7 of CC = 1)
TYP. Unit
125
ns
125
ns
Serial interface
(1) SIOn: n = 1 or 2 (TA = –10 to +70°C, VDD = AVDD = 4.5 to 5.5 V, VSS = AVSS = 0 V)
Parameter
Serial clock cycle time
Serial clock high- and low-level widths
SIn setup time (to SCKn ↑)
SIn hold time (from SCKn ↑ )
SOn output delay time (to SCKn ↓ )
Symbol
tCYSK Input
Output
tWSKH
tWSKL
tSSSK
tHSSK
tDSSK
Input
Output
Condition
External clock
fCLK1/8
fCLK1/16
fCLK1/32
fCLK1/64
fCLK1/128
fCLK1/256
External clock
Internal clock
Remarks 1. fCLK1: operating clock of peripheral circuit (8 MHz)
2. n = 1 or 2
MIN.
MAX. Unit
1.0
µs
1.0
µs
2.0
µs
4.0
µs
8.0
µs
16
µs
32
µs
420
ns
tCYSK/2 – 50
ns
100
ns
400
ns
0
300
ns
(2) SIO2 only (TA = –10 to +70°C, VDD = AVDD = 4.5 to 5.5 V, VSS = AVSS = 0 V)
Parameter
SCK2(8) ↑→STRB ↑
Strobe high-level width
BUSY setup time
(to BUSY detection timing)
BUSY hold time
(to BUSY detection timing)
BUSY inactive →SCK2(1) ↓
Symbol
tDSTRB
tWSTRB
tSBUSY
tHBUSY
tLBUSY
Condition
MIN.
tWSKH
tCYSK – 30
100
MAX.
tCYSK
tCYSK + 30
Unit
ns
ns
100
ns
tCYSK + tWSKH
Remarks 1. The value in parentheses following SCK2 indicates the number of SCK2.
2. BUSY is detected after the time (n+2) x tCYSK (n = 0, 1, and so on) has elapsed relative to SCK2 (8) ↑.
3. BUSY inactive →SCK2 (1) ↓ is the value when data write to SIO2 has been completed.
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