UPD70F3114 Datasheet, PDF (681/692 Pages) NEC – 32-Bit Single-Chip Microcontrollers

APPENDIX C INSTRUCTION SET LIST
(4/5)
Mnemonic Operands
Opcode
Operation
Execution Clock
Flags
i
r
I CY OV S Z SAT
RETI
SAR
0 0 0 0 0 1 1 1 1 1 1 0 0 0 0 0 if PSW.EP = 1
0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 then PC ← EIPC
PSW ← EIPSW
else if PSW.NP = 1
then PC ← FEPC
PSW ← FEPSW
else PC ← EIPC
PSW ← EIPSW
4
4
4
RRRRR
reg1, reg2
r r r r r 1 1 1 1 1 1 R R R R R GR[reg2] ← GR[reg2] arithmetically shift right by
0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 GR[reg1]
1 1 1 ×0 ××
imm5, reg2 r r r r r 0 1 0 1 0 1 i i i i i GR[reg2] ← GR[reg2] arithmetically shift right by zero- 1
1
1
×
0
×
×
extend (imm5)
SASF
cccc, reg2
r r r r r 1 1 1 1 1 1 0 c c c c if conditions are satisfied
0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 then GR[reg2] ← (GR[reg2] Logically shift left by 1)
OR 00000001H
else GR[reg2] ← (GR[reg2] Logically shift left by 1)
OR 00000000H
1
1
1
SATADD reg1, reg2 r r r r r 0 0 0 1 1 0 R R R R R GR[reg2] ← saturated (GR[reg2] + GR[reg1])
1 1 1 ×××××
imm5, reg2 r r r r r 0 1 0 0 0 1 i i i i i GR[reg2] ← saturated (GR[reg2] sign-extend (imm5)) 1
1
1
×
×
×
×
×
SATSUB reg1, reg2 r r r r r 0 0 0 1 0 1 R R R R R GR[reg2] ← saturated (GR[reg2] − GR[reg1])
1 1 1 ×××××
SATSUBI imm16, reg1, r r r r r 1 1 0 0 1 1 R R R R R GR[reg2] ← saturated (GR[reg1] − sign-extend
reg2
i i i i i i i i i i i i i i i i (imm16)
1 1 1 ×××××
SATSUBR reg1, reg2 r r r r r 0 0 0 1 0 0 R R R R R GR[reg2] ← saturated (GR[reg1] − GR[reg2])
1 1 1 ×××××
SETF
SET1
SHL
cccc, reg2
r r r r r 1 1 1 1 1 1 0 c c c c if conditions are satisfied
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 then GR[reg2] ← 00000001H
else GR[reg2] ← 00000000H
1
1
1
bit#3, disp16 0 0 b b b 1 1 1 1 1 0 R R R R R adr ← GR[reg1] + sign-extend (disp16)
3
3
3
×
[reg1]
d d d d d d d d d d d d d d d d Z flag ← Not (Load-memory-bit (adr, bit#3))
Note 3 Note 3 Note 3
Store-memory-bit (adr, bit#3, 1)
reg2, [reg1] r r r r r 1 1 1 1 1 1 R R R R R adr ← GR[reg1]
3
3
3
×
0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 Z flag ← Not (Load-memory-bit (adr, reg2))
Note 3 Note 3 Note 3
Store-memory-bit (adr, reg2, 1)
reg1, reg2 r r r r r 1 1 1 1 1 1 R R R R R GR[reg2] ← GR[reg2] logically shift left by GR[reg1]
1
1 1 ×0 ××
000000001100000 0
imm5, reg2
r r r r r 0 1 0 1 1 0 i i i i i GR[reg2] ← GR[reg2] logically shift left
by zero-extend (imm5)
1 1 1 ×0 ××
SHR
SLD.B
reg1, reg2 r r r r r 1 1 1 1 1 1 R R R R R GR[reg2] ← GR[reg2] logically shift right by GR[reg1] 1
1
1
×
0
×
×
000000001000000 0
imm5, reg2
r r r r r 0 1 0 1 0 0 i i i i i GR[reg2] ← GR[reg2] logically shift right
by zero-extend (imm5)
1 1 1 ×0 ××
disp7[ep],
reg2
r r r r r 0 1 1 0 d d d d d d d adr ← ep + zero-extend (disp7)
GR[reg2] ← sign-extend (Load-memory (adr, Byte))
1
1 Note 9
SLD.BU
SLD.H
disp4[ep],
reg2
disp8[ep],
reg2
r r r r r 0 0 0 0 1 1 0 d d d d adr ← ep + zero-extend (disp4)
Note 18 GR[reg2] ← zero-extend (Load-memory (adr, Byte))
r r r r r 1 0 0 0 d d d d d d d adr ← ep + zero-extend (disp8)
Note 19 GR[reg2] ← sign-extend (Load-memory (adr,
Halfword))
1
1 Note 9
1
1 Note 9
User’s Manual U15195EJ5V0UD
681